[ { "id": 22217, "name": "Mobius Materials", "slug": "mobius-materials", "former_names": [ "Mobius" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/f5f5b865f74e9a6fdbf9dc7d71885ecdea75b962.png", "website": "https://www.mobiusmaterials.com", "all_locations": "San Francisco, CA, USA", "long_description": "Mobius is the safe spot market for electronic components like microcontrollers and capacitors. We help electronics manufacturers buy and sell chips quickly, safely & at market prices. ", "one_liner": "The spot market for semiconductors", "team_size": 6, "industry": "Industrials", "subindustry": "Industrials -> Manufacturing and Robotics", "launched_at": 1732044079, "tags": [ "Hardware", "Manufacturing", "Supply Chain", "Semiconductors" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2020", "status": "Active", "industries": [ "Industrials", "Manufacturing and Robotics" ], "regions": [ "United States of America", "America / Canada", "Remote", "Partly Remote" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/mobius-materials", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2020/mobius-materials.json", "year_founded": 2020, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/mobius-materials/?viewAsMember=true", "x_url": "https://twitter.com/mobiusmaterials", "fb_url": "https://www.facebook.com/mobiusmaterials", "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/f5f5b865f74e9a6fdbf9dc7d71885ecdea75b962.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Gustaf Alstromer", "url": "https://www.ycombinator.com/people/gustaf-alstromer" }, "founders": [ { "user_id": 358908, "full_name": "Margaret Upshur", "title": "Founder", "founder_bio": "Margaret is the CEO and founder of Mobius Materials, a marketplace where manufacturers can buy and sell chips quickly, safely & at market prices. Previously, she led operations at Particle, a SF based electronics company, building a 40 person multinational team that launched 170 different products and shipped millions of units. She also worked at McKinsey where she consulted on manufacturing applications and helped open an office in Kenya. Margaret has an engineering degree from Duke.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/margaretupshur/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/f278b67ed87d66ce05d2da733260523ff279a853.jpg" } ], "jobs": [], "news": [], "launches": [] }, { "id": 28841, "name": "Baud", "slug": "baud", "former_names": [ "Neuralyze", "Cerelyze", "Zener", "Front", "Zener", "SuperCraft", "Ponder", "SuperCraft", "Baud Labs" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/2ea89d0878c367c79b3a58c19eb1323a648e3f38.png", "website": "https://baudlabs.ai", "all_locations": "San Francisco, CA, USA", "long_description": "Novel AI hardware built from first principles to let companies train, fine-tune, and deploy frontier models with orders of magnitude better performance than incumbents", "one_liner": "AI chips for ultra-fast training and inference", "team_size": 3, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1688534176, "tags": [ "Hard Tech", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/baud", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/baud.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/baud-labs-ai/", "x_url": "", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/2ea89d0878c367c79b3a58c19eb1323a648e3f38.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Diana Hu", "url": "https://www.ycombinator.com/people/diana-hu" }, "founders": [ { "user_id": 1348413, "full_name": "Sarang Zambare", "title": "Founder/CEO", "founder_bio": "Multi-time founder with 4 patents and 7+ years in deep learning and AI hardware. ML lead for Peloton Guide from concept to 100,000+ devices shipped. Previously founding ML engineer at Peloton and Caper (acquired by Instacart). Also a certified pilot.", "is_active": true, "linkedin_url": "https://linkedin.com/in/sarang-zambare", "x_url": "https://twitter.com/sarangz11", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/d9ae5ac000c0c036f4b5022a8dd94a1b90a9e2a9.jpg" }, { "user_id": 3805085, "full_name": "Eric Taylor", "title": "Founder & Chief Hardware Architect", "founder_bio": "Experienced ASIC Architect with over a decade of industry experience, including four tape-outs, two major IP releases, two patents, and a publication. Prior roles at NVIDIA, Freescale/NXP, Arteris IP, and Enfabrica.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/eric-taylor-995b923b/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/54e1b3deed285b11303c26e69ac744fbf80d5f4c.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 104577, "title": "Baud - AI Chips for Accelerated Training and Inference", "tagline": "Novel AI hardware and developer platform, co-designed from first principles to let businesses create frontier models with orders of magnitude better performance than incumbents", "body": "**TL;DR**\n\nBaud is building a new chip for training and inference of large AI models\n\nWe have developed a new arithmetic representation of neural networks that does not contain multiplications. Our silicon is architected specifically for this representation and doing this lets us train and serve AI faster and more efficiently than incumbents.\n\n![uploaded image](/media/?type=post&id=104577&key=user_uploads/1348413/43bfbd38-2274-4963-b225-3714d18f7c65)\n\n\\\n\\\n**Our Team** \n\n* **Sarang Zambare**, multi-time founder with 4 patents and 7+ years in deep learning and AI hardware. ML lead for Peloton Guide from concept to 100,000+ devices shipped and founding engineer at Caper (acquired by Instacart) building edge deep learning models.\n* **Eric Taylor**, ex-NVIDIA chip design veteran with a decade of experience including 4 tape-outs on leading process nodes, two major IP releases, multiple patents and publications, prior roles at NVIDIA, Freescale/NXP, Arteris IP, and Enfabrica.\n\n\\\n\\\n**The Problem**\n\nWe are living in exciting times where humanity has figured out a way to turn sand and sunlight into machines of scientific discovery.\n\nBut creating and serving these machines aka frontier AI models, is extremely capital intensive.\n\nNVIDIA’s publicly documented training recipe of the Nemotron model took **6144 H100 GPUs**, going on for around 3 months, drawing around **4.3 megawatts** of electricity.\n\n![uploaded image](/media/?type=post&id=104577&key=user_uploads/1348413/eddfed11-11fd-41b3-bbc2-8bb950078002)\n\nThat's **$44M in rentals or $245M in capex** plus an ungodly number of developer hours standing up distributed training. Models like Claude Opus 4.6 surprised the world, and that's just the beginning. But at these numbers, **only a handful of teams on Earth control the frontier in AI** and have a shot at a new opus-level moment in other domains like robotics, world models, drug discovery, material science, physics, simulation, the list goes on.\\\n\\\nCurrent attempts at solving this such as Cerebras, Groq, Etched, D-Matrix and 50 other chip startups are only attacking the silicon side and leaving the fundamental math side of the problem untouched, because they are focused on inference and hence have to run existing model weights.\n\nWhen we looked deeper, we found that if you let go of the constraint of running existing model weights, a radically different silicon architecture becomes possible, with an order of magnitude better performance.\n\nWe think we're just scratching the surface of what's possible when you co-design the hardware with the model architecture.\n\nAnd that’s what we are betting the farm on.\n\n**Solution**\n\nWe have developed a new way to represent neural network architectures that eliminates multiplications from both the forward and backward passes, and also compresses the weights by more than 10x without any loss in intelligence. The catch is that you need to train the model in this representation, or start with a base model that is also in this representation.\n\nBoth during training and inference, our chip does not need multiplier circuits.\n\nThis makes our individual cores drastically smaller and simpler than say GPU’s tensor cores or the PEs in TPU’s systolic arrays.\n\nWhich means we can pack way more compute and SRAM on the die and move way more weights for the same memory bandwidth.\n\nThis makes our chip faster, less power hungry and simpler to build.\\\n\\\nWe provide a developer platform based on our hardware that makes creation of frontier AI frictionless and economical to serve, so businesses of all sizes can start owning their intelligence.\\\n\\\n**We are live already**\n\n![uploaded image](/media/?type=post&id=104577&key=user_uploads/1348413/fb27985c-5941-4f2b-aac1-a81378047b7c)\n\nOur first chip is validated on the Global Foundries 12nm process and on schedule for tape-out by the end of this year.\\\n\\\nOur training and inference service is already live on a cluster of FPGAs running the chip architecture in emulation.\\\n\\\nUsing FPGA emulation, we've developed a compiler and a distributed training stack that converts any PyTorch exportable model to our format with bit exact results in most cases, including popular opensource architectures such as GLM, Qwen, Gemma, DeepSeek, Flux, Wan and others.\\\n\\\nYou can checkout a small demo of our chip running in emulation on a single FPGA here: \n\n**Our partner program**\\\n\\\nBaud is now working with design partners who can test our systems and help smooth out the developer experience, in exchange for reserved capacity on our first cluster for training and inference.\\\n\\\nCapacity is limited. Contact us if you are training something new or are tired of paying through the nose for intelligence that you do not own.\\\n\\\n\n\n![uploaded image](/media/?type=post&id=104577&key=user_uploads/1348413/7e141e34-4913-4656-b502-b1b7201eeb73)\n\n", "url": "https://www.ycombinator.com/launches/RCj-baud-ai-chips-for-accelerated-training-and-inference", "votes": 98, "created_at": "2026-07-06T15:52:27.467Z" } ] }, { "id": 28851, "name": "Bronco AI", "slug": "bronco-ai", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/dce0ac1e308aa18998242314db08d5821b4db4aa.png", "website": "https://www.bronco.ai/", "all_locations": "San Francisco, CA, USA", "long_description": "Bronco is an applied AI lab helping chipmakers keep Moore’s law going. Our mission is to build AI silicon verification engineers that find bugs, drive functional coverage, and help companies ship working chips on time.\r\n\r\nWe're currently deployed alongside verification teams at leading chip companies building next generation hardware (4 nm process node).\r\n\r\nWe are well-funded and backed by tier-1 investors, including YC, 8VC, Elad Gil, SV Angel, and Contrary Capital. We have also established strong relationships with the leading academic and industry researchers in the field of AI for chip design. Our advisors have won multiple Best Paper Awards at leading conferences, been cited tens of thousands of times, and received some of the highest honors in the microelectronics and EDA industries.", "one_liner": "AI for ASIC Design Verification", "team_size": 5, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1683953569, "tags": [ "B2B", "Enterprise Software", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2023", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/bronco-ai", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2023/bronco-ai.json", "year_founded": 2023, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/bronco-ai", "x_url": "", "fb_url": null, "cb_url": "https://www.crunchbase.com/organization/bronco-ai", "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/dce0ac1e308aa18998242314db08d5821b4db4aa.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Garry Tan", "url": "https://www.ycombinator.com/people/garry-tan" }, "founders": [ { "user_id": 824475, "full_name": "David Zhi LuoZhang", "title": "Founder", "founder_bio": "Building Bronco AI | Enjoyer of industrials, ML, and the frontier thesis", "is_active": true, "linkedin_url": "https://linkedin.com/in/dluozhang", "x_url": "https://twitter.com/dluozhang", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/8ce5b228a9b2faefce21814be9e26baa231c9e26.jpg" }, { "user_id": 1264576, "full_name": "Jeffrey Pan", "title": "Founder", "founder_bio": "Building Bronco AI, deeply passionate about the industrial economy, AI, and their future together.", "is_active": true, "linkedin_url": "https://linkedin.com/in/jeffreyzpan", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/789018efd16d774289865d77f43b74cde70218c4.jpg" } ], "jobs": [], "news": [], "launches": [] }, { "id": 29010, "name": "Silimate", "slug": "silimate", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/61f4bbb4f45487fb9514316eae7b6e1b1c316a4a.png", "website": "https://www.silimate.com", "all_locations": "San Francisco, CA, USA", "long_description": "We're building AI-native tools & agent-driven workflows for frontend chip design. \r\n\r\nToday, Fortune enterprises and chip unicorns license Silimate to hit their PPA targets and functional closure in days instead of months. With Silimate, chip companies tape out better, more market-competitive chips much more quickly.", "one_liner": "Fast, efficient agents for chip design and debug", "team_size": 8, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1691095117, "tags": [ "Developer Tools", "B2B", "Enterprise Software", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Summer 2023", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/silimate", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2023/silimate.json", "year_founded": 2023, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/silimate", "x_url": "", "fb_url": null, "cb_url": null, "github_url": "https://github.com/Silimate", "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/61f4bbb4f45487fb9514316eae7b6e1b1c316a4a.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Jared Friedman", "url": "https://www.ycombinator.com/people/jared-friedman" }, "founders": [ { "user_id": 1313634, "full_name": "Ann Wu", "title": "Founder", "founder_bio": "Co-founder & CEO of Silimate. Ann designed several generations of custom silicon at Apple, helped manage the inference ASIC programs at Meta, and developed product strategy & execution at an AI chip start-up.", "is_active": true, "linkedin_url": "https://linkedin.com/in/annwuhoo", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/dfc547915f4496607e7258cfc4e7e599b544c122.jpg" }, { "user_id": 1184182, "full_name": "Akash Levy", "title": "Founder", "founder_bio": "Co-founder & CTO of Silimate. Akash has a PhD from Stanford in Electrical Engineering, with technical expertise spanning EDA, AI, and cloud through his time at Synopsys, NVIDIA, and AWS. He has taped out 3 chips, published 14 papers on circuit design, and has two pending patents in the EDA space.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/akashlevy/", "x_url": "https://twitter.com/akashlevy", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/fda997887e28bf5a1fcf455cfa51c65aaeb83b89.jpg" } ], "jobs": [ { "id": 102953, "title": "Chip/EDA/Software Intern", "url": "https://www.ycombinator.com/companies/silimate/jobs/6CTGk7H-chip-eda-software-intern", "location": "Mountain View, CA, US", "type": "Internship", "role": "Engineering", "role_type": "Full stack", "salary_range": "$5.2K - $7K / monthly", "equity_range": "", "experience": null, "visa": "US citizen/visa only", "skills": [] }, { "id": 102954, "title": "Applied AI Engineer", "url": "https://www.ycombinator.com/companies/silimate/jobs/RVX3ulq-applied-ai-engineer", "location": "Mountain View, CA, US / San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Machine learning", "salary_range": "$140K - $220K", "equity_range": "0.50% - 2.00%", "experience": "1+ years", "visa": "Will sponsor", "skills": [] }, { "id": 102955, "title": "Chip/Software Engineer", "url": "https://www.ycombinator.com/companies/silimate/jobs/kxgYCET-chip-software-engineer", "location": "Mountain View, CA, US / San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Full stack", "salary_range": "$140K - $220K", "equity_range": "0.50% - 2.00%", "experience": "1+ years", "visa": "Will sponsor", "skills": [] }, { "id": 102956, "title": "Applied AI Intern", "url": "https://www.ycombinator.com/companies/silimate/jobs/xt2UihN-applied-ai-intern", "location": "Mountain View, CA, US", "type": "Internship", "role": "Engineering", "role_type": "Full stack", "salary_range": "$5.2K - $7K / monthly", "equity_range": "", "experience": null, "visa": "US citizen/visa only", "skills": [] }, { "id": 102957, "title": "AI Research Intern", "url": "https://www.ycombinator.com/companies/silimate/jobs/BUbLN9M-ai-research-intern", "location": "Mountain View, CA, US", "type": "Internship", "role": "Engineering", "role_type": "Full stack", "salary_range": "$5.2K - $7K / monthly", "equity_range": "", "experience": null, "visa": "US citizen/visa only", "skills": [] } ], "news": [ { "title": "Preparing For AI-Driven Chip Design And Verification", "url": "https://semiengineering.com/preparing-for-ai-driven-chip-design-and-verification/", "date": "Jul 27, 2026" }, { "title": "AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions", "url": "https://semiengineering.com/ai-in-chip-design-lots-of-promise-plenty-of-unanswered-questions/", "date": "Jul 15, 2026" }, { "title": "Executive Outlook: Agentic AI's Impact On Chip Design", "url": "https://semiengineering.com/executive-outlook-agentic-ais-impact-on-chip-design/", "date": "Jun 25, 2026" }, { "title": "Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner - SemiWiki", "url": "https://semiwiki.com/semiconductor-services/esd-alliance/370229-agentic-ai-and-the-future-of-chip-design-from-productivity-tool-to-engineering-partner/", "date": "Jun 15, 2026" }, { "title": "Silimate CEO pioneers AI debugger for chip designers", "url": "https://stanforddaily.com/2026/03/11/silimate-ceo-pioneers-ai-debugger/", "date": "Mar 11, 2026" } ], "launches": [ { "id": 73953, "title": "👾 Silimate - Copilot for chip designers", "tagline": "Design the right semiconductors chips in less time", "body": "**TL;DR: Silimate helps chip teams converge to functional correctness and optimized PPA faster, so that they can build better chips in less time.**\n\n# \n\n# **❌ The Problem**\n\nThe world needs specialized semiconductor chips to be built faster for the rapidly-evolving software workloads in datacenters and at the edge.\n\nYet, chip teams today face time- and effort-intensive bottlenecks in converging to functional correctness and optimized PPA (power/performance/area). These bottlenecks account for most of the typical 12-18 month chip development cycle, and impede chip teams’ ability to make important changes to their designs in late project stages — when real, data-driven issues tend to surface from simulations.\n\n# \n\n# **✨ Our Solution**\n\nSilimate finds functional bugs, predicts PPA issues, and recommends real fixes in real-time alongside RTL development. Chip designers get a context-aware RTL companion that helps them write correct, PPA-optimized RTL from the onset, and build better chips in less time.\n\n**We’re live with chip design teams today.**\n\nIf you’re a chip designer or lead a chip design team, we can help you eliminate weeks/months from your design cycles. Reach out to us to schedule a live demo!\n\n# \n\n# **🌎 Why Now**\n\nDeath of Moore’s Law, an explosion of custom chip architectures, geopolitics, talent shortage, massive demand for AI chips, and increasing complexities in advanced chip design – we’re building the critical pickaxe for the AI and edge [silicon renaissance](https://www.forbes.com/sites/robtoews/2020/05/10/artificial-intelligence-is-driving-a-silicon-renaissance/?sh=3566b040553c).\n\n# \n\n# **👋 Contact us at [hello@silimate.com](mailto:hello@silimate.com) to learn more!**\n\n* If you’re a chip designer or lead a chip design team, email us – we’ll help speed up your RTL development cycles.\n* If you’re not a chip designer but know one (or a few), send them our way!", "url": "https://www.ycombinator.com/launches/JEn-silimate-copilot-for-chip-designers", "votes": 65, "created_at": "2023-08-09T16:29:19.599Z" } ] }, { "id": 29472, "name": "Silogy", "slug": "silogy", "former_names": [ "SiLogy" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/01e853c98eeaa75f49024ede178b38c98d3e9a26.png", "website": "https://silogy.io", "all_locations": "New York City, NY, USA; Remote", "long_description": "Silogy is building an AI-powered platform for chip developers to simulate and debug their designs.", "one_liner": "An AI-powered test and debug platform for chip developers", "team_size": 3, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1703691870, "tags": [ "Developer Tools", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Winter 2024", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada", "Remote", "Fully Remote" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/silogy", "api": "https://devasheeshg.github.io/yc-api/batches/winter-2024/silogy.json", "year_founded": 2023, "city": "New York City", "country": "US", "linkedin_url": "https://www.linkedin.com/company/100808053/", "x_url": "", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/01e853c98eeaa75f49024ede178b38c98d3e9a26.png", "app_video_url": null, "dday_video_url": null, "company_photos": [ "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/45641ed250a7c25bb6575334da348f78d132831c.png" ], "primary_partner": { "name": "Brad Flora", "url": "https://www.ycombinator.com/people/brad-flora" }, "founders": [ { "user_id": 1524497, "full_name": "Kay Li", "title": "Founder/CEO", "founder_bio": "Cofounder and CEO of Silogy. Originally a math major, I became passionate about chips while working in high-frequency trading. Previously Hudson River Trading. Interested in all things related to chips and money.", "is_active": true, "linkedin_url": "https://linkedin.com/in/kay-li-84924128b", "x_url": "https://twitter.com/silikayli", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/53c172050432e89256001715aa9248ca895e0fe5.jpg" }, { "user_id": 151331, "full_name": "Paul Kim", "title": "Founder/CTO", "founder_bio": "SiLogy CTO and cofounder. Previously Cloudflare, Sense Talent Labs, United Auto Workers. Interested in all things software, especially EDA.", "is_active": true, "linkedin_url": "https://linkedin.com/in/paul-kim-7b766262", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/7230c73421b6dc3b376bbebd3b9949d8561f46f7.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 79226, "title": "SiLogy: Chip design and verification in the cloud", "tagline": "All-in-one platform for chip and FPGA development teams", "body": "**TL;DR**: SiLogy is building a platform for chip developers to run tests, track test statistics, and collaborate on debugging.\n\n—\n\nHey, we’re [Paul](https://linkedin.com/in/paul-kim-7b766262) and [Kay](https://linkedin.com/in/kay-li-84924128b), the cofounders of [SiLogy](https://silogy.io). We’re building chip design and verification tools to speed up the semiconductor development cycle.\n\n## **The Problem**\n\nInterest in designing new chips is growing, thanks to demand from AI and the predicted decline of Moore’s Law. Since the number of possible states grows exponentially with chip complexity, the need for testing in simulation is exploding, with chip developers already spending 70% of their time on testing. (See this video on the [verification gap](https://www.youtube.com/watch?v=rtaaOdGuMCc)).\n\nTooling hasn’t kept up. The state-of-the-art in collaborative debugging is to walk to a coworker’s desk and point to an error in a log file or waveform file. Each chip company rolls out its own tooling and infra to deal with this—this was Kay’s entire job at his last gig. But they want to work on chips, not devtools! The solutions they come up with are often inadequate and frustrating. That’s why we started SiLogy.\n\n## **The solution**\n\nSiLogy is a web app to manage the entire digital verification workflow. (“Digital verification” means testing the logic of the design and includes everything before the physical design of the chip. It’s the most time-consuming stage in verification.)\n\nWe combine three capabilities:\n\n**Test running, results, and statistics**: Our CI tool runs tests in the cloud, allowing engineering teams unlimited flexibility in scaling their test volume. We also track each project’s progress in test coverage and test pass rate.\n\n![uploaded image](/media/?type=post&id=79226&key=user_uploads/151331/d9a4d2a6-9662-4ee6-8eef-e735b10885b6)\n\n**Killer application-specific features**: We’re building features tailored for verification use cases. We incorporate a test orchestration framework, waveform viewer, coverage report, and other features specifically for verification teams, providing customers an advantage over competitors using a generic CI solution such as Jenkins.\n\n![uploaded image](/media/?type=post&id=79226&key=user_uploads/151331/d2beb46c-884b-4fec-b731-698c1c0a2312)\n\n**Collaboration**: soon you’ll be able to send a link to and leave a comment on a specific location within a log or waveform file, just like in Google Docs.\n\n![uploaded image](/media/?type=post&id=79226&key=user_uploads/151331/db8f1954-dafb-4a9e-b739-1b883c4963ac)\n\n## **Asks**\n\nIf you have experience with Verilog, even just from college, give our product a try at . Tell your loved ones who work on chip or FPGA design and verification to give us a try as well.\n\nIf you have thoughts on the state of verification, get in touch at [paul@silogy.io](mailto:paul@silogy.io). If you or someone you know wants a demo, schedule a meeting with us [here](https://calendly.com/d/5gd-rf6-66h/silogy-product-demo).\n\nThanks for your support!", "url": "https://www.ycombinator.com/launches/Kbq-silogy-chip-design-and-verification-in-the-cloud", "votes": 29, "created_at": "2024-03-08T22:44:21.395Z" } ] }, { "id": 29662, "name": "Atum Works", "slug": "atum-works", "former_names": [ "phorg", "ATUM WORKS", "ATUM Works" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/919432869b9d7a01cb7d24ccff7380278318f625.png", "website": "https://atum.works/", "all_locations": "San Francisco, CA, USA", "long_description": "", "one_liner": "Gigascale Nanomanufacturing", "team_size": 3, "industry": "Industrials", "subindustry": "Industrials -> Manufacturing and Robotics", "launched_at": 1745346268, "tags": [ "Hard Tech", "3D Printing", "Semiconductors" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Spring 2025", "status": "Active", "industries": [ "Industrials", "Manufacturing and Robotics" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/atum-works", "api": "https://devasheeshg.github.io/yc-api/batches/spring-2025/atum-works.json", "year_founded": 2024, "city": "San Francisco", "country": "US", "linkedin_url": "https://linkedin.com/company/atum-works", "x_url": "https://twitter.com/atumworks", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/919432869b9d7a01cb7d24ccff7380278318f625.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Garry Tan", "url": "https://www.ycombinator.com/people/garry-tan" }, "founders": [ { "user_id": 1884492, "full_name": "Lucas Pabarcius", "title": "Founder/CEO", "founder_bio": ".", "is_active": true, "linkedin_url": "www.linkedin.com/in/lucas-pabarcius-ba3595167", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/0884df112dcac548a238f88c861cec72db25ca32.jpg" }, { "user_id": 1975891, "full_name": "Matteo Kimura", "title": "Founder/CRO", "founder_bio": ".", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/matteo-kimura-90879318b/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/e889b9ac0bec382d4d511226cf89459d675ae771.jpg" }, { "user_id": 1884437, "full_name": "Malcolm Tisdale", "title": "Founder/COO", "founder_bio": ".", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/malcolm-tisdale", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/3589b15041b76034e67feec70fa57fba14af2c76.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 89753, "title": "Atum Works", "tagline": "3D Lithography Foundry", "body": "\n\n**Problem**\n\n“For the past 50 years, semiconductor-technology development has felt like walking inside a tunnel. The road ahead was clear, as there was a well-defined path. And everyone knew what needed to be done: shrink the transistor. Now, we have reached the end of the tunnel.\"\\\nH.-S. Philip Wong, Chief Scientist, TSMC, 2024.\n\nToday’s 2D lithography has hit a fundamental wall in feature density, so the semiconductor industry has begun stacking 2D layers to fit more transistors, bits, and bandwidth on each chip. \\\n\\\nBut stacking scales cost exponentially with density, unlike the constant cost days of Moore: a 10-layer high bandwidth memory (HBM) package is \\~5x more expensive than the same amount of un-stacked DRAM.\n\n**Solution**\n\nUsing a 3D process to make today's increasingly 3D integrated circuits could shortcut this problem, scaling process complexity with materials rather than layers and enabling the next decade of continued progress.\n\nOur 3D lithography technology can do this: it is capable of fabricating multi-material 3D structures with 100 nm resolution at wafer scale.\n\nWhere the ability to create more complex forms enables more complex functions, such granular control of matter enables the future of much more than just chips, including biotech, sensing, and advanced materials.\n\nWe recently crossed the cost thresholds that make this technology commercially viable. We will be driving an exponential scaling law in the production capacity of this technology over the coming decade.\n\n**Team**\n\n![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXcMsUlRx_bo7xJvNWmZaC-39OI7Hknw0Y65Er2tjyUh54Sd4--EgCih-wQzZojhTUdUgn2OqKfPxVzmnfqnJGprg2qacYS56K-eYqnSh_n3uz75XB9uyCslMaxReWdNHhKkcVHF?key=cch75ExUod4AOIuWU2xY6A)\n\nWe’re a team of physicists and systems engineers from Caltech and NASA, where we previously matured multiple nascent technologies, winning NASA’s Most Visionary Concept and Best Product Development awards.\\\n\\\n**Advisory Board**\\\nDr. H.-S. Philip Wong: Chief Scientist, TSMC
\\\nDr. Eli Yablonovitch: Director Emeritus of the NSF Center for Energy Efficient Electronics Science (E3S)\\\nDr. Julia Greer: Director, Caltech Kavli Nanoscience Institute
 
\\\nDr. Michael Hochberg: Silicon Photonics Pioneer
\\\nDr. Pooya Tadayon: Intel Fellow
", "url": "https://www.ycombinator.com/launches/NLd-atum-works", "votes": 87, "created_at": "2025-04-22T18:46:21.407Z" } ] }, { "id": 29672, "name": "DeepSim, Inc.", "slug": "deepsim-inc", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/4d2d742eff5354c7ab2613bb9ba4ba6a64e707b5.png", "website": "https://www.deepsim.io", "all_locations": "San Francisco, CA, USA", "long_description": "DeepSim is building an AI physics simulator. We are currently developing the only thermal simulator to meet AI chip design needs and are validating our tool with Intel. We are a team of three electrical engineering PhDs from Stanford with backgrounds in semiconductor fabrication and design.", "one_liner": "An AI physics simulator for AI chip design", "team_size": 7, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1723754775, "tags": [ "B2B", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2024", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada", "Remote", "Partly Remote" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/deepsim-inc", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2024/deepsim-inc.json", "year_founded": 2020, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/deepsim-inc/", "x_url": "", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/4d2d742eff5354c7ab2613bb9ba4ba6a64e707b5.png", "app_video_url": null, "dday_video_url": null, "company_photos": [ "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/0d2e1a9bc67f541baed33d9188044d4518866854.png" ], "primary_partner": { "name": "David Lieb", "url": "https://www.ycombinator.com/people/david-lieb" }, "founders": [ { "user_id": 1869533, "full_name": "Connor McClellan", "title": "Founder/CEO", "founder_bio": "Stanford EE PhD grad now building an AI physics simulation platform at DeepSim to solve the frustrating parts of my PhD. I'm also really into espresso making and will be happy to make you your best cup of coffee.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/connor-j-mcclellan", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/e777414bf669acbc8f3f05cda28345517e5cce21.jpg" }, { "user_id": 1991480, "full_name": "Alexander Gabourie", "title": "Founder/CTO", "founder_bio": "Alex is a co-founder of DeepSim, Inc., where he develops AI physics simulators. He earned his PhD in Electrical Engineering from Stanford, specializing in nanoscale thermal simulations, and brings over a decade of experience in the semiconductor industry.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/alexgabourie/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/3e26de1d3e0b56d0a2f385f73a269c4b5fcc9de6.jpg" }, { "user_id": 1993598, "full_name": "Chuck Koroglu", "title": "Founder", "founder_bio": "Stanford EE PhD with background in semiconductor engineering, and physics modeling of integrated circuits. Excited about transforming the landscape of engineering simulations with new technology that combines physics, experimental data and AI.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/ckoroglu/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/46cd7b4aa170ce4fac91a1109d64cbe7b49d976a.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 83111, "title": "DeepSim – AI physics simulations", "tagline": "Run complex physics simulations signficantly faster than any commerical tool.", "body": "**TLDR:** AI-accelerated 3D physics simulator for engineers\n\n[DeepSim](https://www.deepsim.io/) makes it easy for engineers to run 3D physics simulations fast. This means rapid design iterations for better products and real-world monitoring for better decisions.\n\nWe built a new physics simulation platform that leverages AI physics models for very fast, ultra-scalable physics simulations.\n\n—\n\nHi everyone! We are [Connor,](https://www.linkedin.com/in/connor-j-mcclellan/) [Alex,](https://www.linkedin.com/in/alexgabourie/) and [Chuck,](https://www.linkedin.com/in/ckoroglu/) and we love physics simulations. While working on our PhDs at Stanford, we saw how physics simulators needed a refresh to solve modern problems. That’s why we started [DeepSim.](https://www.deepsim.io/)\n\n## The Problem\n\nRunning 3D physics simulations is **difficult**, **expensive**, and **slow**.\n\n1. **Setup:** Experienced engineers still spend countless hours meshing their designs before even running a single simulation.\n2. **Run:** Many simulations take hours to even weeks on expensive compute systems. Some are even intractable and require highly trained engineers to simplify the problems at a significant cost of accuracy.\n3. **Attention:** Each step requires constant babysitting as simulators are fragile and can fail at any time.\n\n🧑‍🔧️ Engineers hate the tedious simulation setup and wasted time due to failed simulations.\\\n👔 Managers hate that engineers can’t go faster and use tons of cloud credits.\\\n💰 CEOs/VPs hate that engineering delays stall a product launch.\n\n## The Solution\n\nLeverage AI to **simplify**, **speed up**, and **scale up** 3D physics simulations.\n\nWe are building a new AI physics simulation platform, automating away the physics setup and simulating designs 1000X faster with no drop in accuracy.\n\nOur platform uses lightweight, easy-to-train AI models combined with a powerful GPU-accelerated solver to deliver solutions quickly and efficiently. This approach eliminates the bulkiness of traditional finite element method (FEM) tools and overcomes the inflexibility of other AI physics simulators.\n\n![uploaded image](/media/?type=post&id=83111&key=user_uploads/1869533/6218d9cd-39b9-4307-a144-9f346d8d3c65)\n\nAt [DeepSim](https://www.deepsim.io/), we have already worked with semiconductor companies to build the most powerful thermal simulator for circuit design, running thermal simulations with billions of nodes in minutes on a single GPU, which is 1000X more detail than a commercial tool can deliver using 50+ CPU cores in the same amount of time.\n\nWith DeepSim's simulator, we are able to model extremely complex geometries with length scales spanning 6 orders of magnitude, intractable to solve with FEM tools. Below is a thermal simulation of an integrated circuit, complete with a heat sink and airflow, that only took 10 minutes to run. We can resolve hot spots in individual transistors (\\~10 nm in size) within a whole chip (1 cm).\n\n![uploaded image](/media/?type=post&id=83111&key=user_uploads/1869533/26e48815-e3db-4cfa-bdd4-52168c537546)\n\n## Use Cases\n\nThis is a breakthrough in 3D physics simulations that empowers engineers in the same way FEM did 50 years ago. We’re excited to see where engineers take our tool!\n\nSome initial use cases are:\n\n* Speeding up the design of complex systems with faster simulations\n* Utilizing design automation to speed up development\n* Developing digital twins for system operation\n\n## The Team\n\n![uploaded image](/media/?type=post&id=83111&key=user_uploads/1869533/c032c745-4faf-4374-8a43-92de0645a397)\n\nChuck, Alex, and Connor founded DeepSim to solve the frustrating parts of their PhDs.\n\n## The Ask\n\nWe would love to talk with engineers that…\n\n* design and operate battery packs for EVs or grid-scale energy storage\n* design and deploy satellites\n* work on thermal management of semiconductors, from the chip scale to data centers\n* have any complaints about slow or frustrating simulations\n\nContact us at [founders@deepsim.io](mailto:founders@deepsim.io)!", "url": "https://www.ycombinator.com/launches/LcV-deepsim-ai-physics-simulations", "votes": 35, "created_at": "2024-08-16T04:14:43.665Z" } ] }, { "id": 29754, "name": "Conductor Quantum", "slug": "conductor-quantum", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/6f87b0dddb05a92646b51780f21648d12f3019bf.png", "website": "https://www.conductorquantum.com", "all_locations": "San Francisco, CA, USA", "long_description": "Conductor Quantum is building quantum superintelligence: AI that operates quantum computers to make scientific discoveries beyond human reach.\r\n\r\nQuantum computers let us understand the world at its most fundamental level, the path to new drugs, new materials, and discoveries no human can reach alone. \r\n\r\nA quantum computer is the perfect simulator of nature: it encodes the logic of reality into a programmable machine, atom by atom, electron by electron. Give AI that simulator and you open the door to discovery.\r\n\r\nThe bottleneck is operating the hardware. Today, engineers spend days or weeks by hand to bring a chip to operating conditions for just two qubits. A qubit is the information-carrying unit of a quantum computer, the equivalent of a bit in a classical one, and a useful machine needs billions. \r\n\r\nRemoving the human from that loop is only half the problem. Every command an AI sends to a quantum computer must be optimised for the specific hardware it runs on.\r\n\r\nWe build the AI that operates quantum computers and tunes every machine it runs on. That is the path to quantum superintelligence.", "one_liner": "AI that operates quantum computers for scientific discovery", "team_size": 4, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1718219316, "tags": [ "Hard Tech", "Machine Learning", "Quantum Computing", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Summer 2024", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": [ { "question": "What is your long-term vision? If you truly succeed, what will be different about the world?", "answer": "Everyone will have access to a quantum computer from their desk." } ], "url": "https://www.ycombinator.com/companies/conductor-quantum", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2024/conductor-quantum.json", "year_founded": 2024, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/conductorquantum/", "x_url": "https://twitter.com/conductorquant", "fb_url": null, "cb_url": null, "github_url": "https://github.com/conductorquantum", "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/6f87b0dddb05a92646b51780f21648d12f3019bf.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Tom Blomfield", "url": "https://www.ycombinator.com/people/tom-blomfield" }, "founders": [ { "user_id": 1977732, "full_name": "Brandon Severin", "title": "Founder/CEO", "founder_bio": "Building quantum superintelligence.\n\nDuring my PhD at Oxford, I worked with 4 quantum institutions across the globe (IST Austria, Basel, UNSW, Diraq), developing AI for semiconductor quantum device control and published 4 papers on the topic including one in Nature. \n", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/brandon-severin/", "x_url": "https://twitter.com/BrandonSeverin", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/87d24eacb09bbfa920e690defd179aa0cfe720b2.jpg" }, { "user_id": 947594, "full_name": "Joel Pendleton", "title": "Founder/CTO", "founder_bio": "Co-founder of Conductor Quantum, building software for quantum computers. I’ve worked at many deep tech startups and research labs, exploring various quantum computing technologies — from carbon nanotubes to superconducting transmon qubits. I left my PhD at Oxford to start Conductor Quantum.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/joelpendleton/", "x_url": "https://twitter.com/joelpendleton", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/eec48af10146303ada5db62e00483a97d82d86a9.jpg" } ], "jobs": [ { "id": 76007, "title": "Quantum Engineer (Spin)", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/mvfbgvb-quantum-engineer-spin", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "$120K - $180K", "equity_range": "0.25% - 1.50%", "experience": "1+ years", "visa": "US citizen/visa only", "skills": [ "Python", "Design systems" ] }, { "id": 90538, "title": "Quantum Engineer (Superconducting)", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/Gcnhe4e-quantum-engineer-superconducting", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "$120K - $180K", "equity_range": "0.25% - 1.50%", "experience": "1+ years", "visa": "US citizen/visa only", "skills": [ "Python" ] }, { "id": 92445, "title": "AI Systems Engineer", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/bVWYarJ-ai-systems-engineer", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Full stack", "salary_range": "$120K - $180K", "equity_range": "0.25% - 1.50%", "experience": "Any (new grads ok)", "visa": "US citizen/visa only", "skills": [ "Amazon Web Services (AWS)", "Microsoft Azure", "Google Cloud", "Python", "Redis", "Machine Learning", "Reinforcement learning (RL)", "Design systems", "Next.js", "FPGAs" ] }, { "id": 102431, "title": "Quantum Engineer (Neutral Atom)", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/SjZPBMm-quantum-engineer-neutral-atom", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "$120K - $180K", "equity_range": "0.25% - 1.50%", "experience": "1+ years", "visa": "US citizen/visa only", "skills": [ "Python" ] }, { "id": 102432, "title": "Quantum Engineer (Ion Trap)", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/eV4F5ew-quantum-engineer-ion-trap", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "$120K - $180K", "equity_range": "0.25% - 1.50%", "experience": "1+ years", "visa": "US citizen/visa only", "skills": [ "Python" ] }, { "id": 103103, "title": "Executive Assistant / Lab Operations Manager", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/1vOd00H-executive-assistant-lab-operations-manager", "location": "Albuquerque, NM, US", "type": "Full-time", "role": "Operations", "role_type": null, "salary_range": "$55K - $75K", "equity_range": "0.05% - 0.15%", "experience": "Any (new grads ok)", "visa": "US citizen/visa only", "skills": [ "Python" ] }, { "id": 104396, "title": "AI Systems Engineer (NM)", "url": "https://www.ycombinator.com/companies/conductor-quantum/jobs/OjWoAtF-ai-systems-engineer-nm", "location": "Albuquerque, NM, US", "type": "Full-time", "role": "Engineering", "role_type": "Full stack", "salary_range": "$75K - $125K", "equity_range": "0.25% - 1.50%", "experience": "Any (new grads ok)", "visa": "US citizen/visa only", "skills": [] } ], "news": [], "launches": [ { "id": 97009, "title": "Coda — Natural language quantum computing", "tagline": "Describe your problem and execute it on real quantum computers.", "body": "![uploaded image](/media/?type=post&id=97009&key=user_uploads/1977732/6b78d7ee-645f-420a-8e65-86a4e4da0982)\n\n**_TL;DR Quantum computing will not scale if every program is a hand-written circuit. The future is describing what you want a quantum computer to do and letting the system handle the rest._**\n\nHi - We are Brandon and Joel from Conductor Quantum.\n\nWe’re announcing Coda - our natural language interface for quantum computing.\n\nQuantum computers offer a new computing paradigm for simulating the world at the atomic level. This opens up new possibilities in chemistry, materials science, and drug discovery that push beyond what the largest classical supercomputers can handle.\n\n## Problem\n\nUsing quantum computers today requires deep domain expertise and low-level tooling.\n\n## Solution\n\n\n\nType your problem into a box, Coda builds the quantum circuit, verifies the code and runs it on current state-of-the-art quantum computers.\n\nIf you’re completely new to quantum, we’ve included a learn mode to get you started. One of the first quantum computers we’re offering on our platform is [Rigetti’s (S14)](https://www.ycombinator.com/companies/rigetti-computing) 84-qubit quantum computer. We also support simulations up to 34 qubits supported by NVIDIA cu-Quantum.\n\n## Why?\n\nWe’re building Coda because we want everyone to be able to access a quantum computer from their desk, as soon as possible.\n\n## What we’ve achieved so far\n\n* Built the first API for low-level silicon quantum chip control.\n* Partnered with quantum chip maker SemiQon and ran our software across 64 of their quantum devices.\n* Shipped quantum control software for companies including Quobly and EeroQ.\n\n## What’s next?\n\n* End-to-end GPU + QPU orchestration, so classical and quantum computation work together in a single workflow.\n* Connecting Coda to our lower-level quantum control and tune-up software, closing the loop from high-level intent to device-level execution.\n* Pushing our control software to larger numbers of qubits as hardware scales.\n\n## Team\n\n![uploaded image](/media/?type=post&id=97009&key=user_uploads/1977732/fca09063-084c-4734-b9ec-0edde6ec9dd3)\n\n[Brandon](https://www.linkedin.com/in/brandon-severin/), CEO, Previously a postdoc at Oxford, with multiple Nature journal publications on silicon quantum computing. Developed early AI systems for automated qubit formation. PhD, Oxford.\n\n[Joel](https://www.linkedin.com/in/joelpendleton/), CTO, Built machine-learning–based control software for superconducting qubits at QuantrolOx, with prior roles at Quantum Motion and C12. MSc Physics, UCL. Left machine learning and quantum computing PhD at Oxford to start Conductor.\n\n[Raymond](https://www.linkedin.com/in/raymond-jow-190654145/), Founding Engineer, Former SpaceX guidance, navigation, and control software engineer whose code flew on 100+ Falcon 9 missions. Previously worked on robotics at NASA and quantum machine learning at Cornell. BS Physics and Computer Science, Harvard.\n\n## Asks\n\n* Join our team. We’re looking for hardcore full-stack quantum engineers who want to work across the entire stack - from device fabrication, fridge wiring to qubit operation. As well as engineers focused on quantum algorithms and applications.\n* Intros to companies based on hard science - think pharma, biotech, materials, chemistry, engineering who are interested in leveraging quantum computing in their workflows.\n* Email us at [founders@conductorquantum.com](mailto:founders@conductorquantum.com) \n* Try Coda here: [https://coda.conductorquantum.com/](https://coda.conductorquantum.com/login)", "url": "https://www.ycombinator.com/launches/PEf-coda-natural-language-quantum-computing", "votes": 10, "created_at": "2026-01-21T17:45:59.744Z" }, { "id": 83306, "title": "Conductor Quantum - Quantum computers on silicon chips using AI", "tagline": "Our AI software creates qubits 1000x faster than current methods.", "body": "**Tl;dr:**\n\n* [Conductor Quantum](https://www.conductorquantum.com) is using **AI software** to **create qubits** in **semiconductor chips** to **build quantum computers** at scale.\n* The two founders met during their **PhDs at Oxford**. They have experience at 5 quantum companies and institutions, plus 4 publications between them.\n* Conductor Quantum is launching **the first publicly available API** to **classify quantum transport features in semiconductors**.\n\n# **🧑‍🔬🧑‍💻The Team**\n\nHi - We are Brandon and Joel! We are building Conductor Quantum.\n\n![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXdZn6_SJC2SQu80WOKYWfJsFE9MCQt2R9PXG6mXNMb3co5B6iBYNZ7ckJ8i8Mgd01fTALt1oZeeLzN19Lc68mTVIqnZZZeJjPQVt_I6ilRcz1m8J-WB-L3xn-zcN4Hci1MBDC6UggpvjN13o_5EMAk3hCWM?key=M7s5FyBBuze--OVSs9y0AQ)\n\nCEO, [Brandon](https://www.linkedin.com/in/brandon-severin/) – Brandon developed **_AI for Quantum Computing in Silicon_** during his **PhD** at **Oxford**. Over the past four years, Brandon has worked with four top quantum research institutions on **software for quantum device control** and has **four publications**, including one in **Nature**.\n\nCTO, [Joel](https://www.linkedin.com/in/joelpendleton/) – Joel has shipped software at **four deep tech companies** and has worked with a series of quantum devices ranging from **carbon nanotubes to superconducting circuits**. Joel studied **Physics at UCL** and **dropped out of his PhD** at **Oxford** to start Conductor Quantum.\n\nDuring Joel’s PhD at **Oxford**, he launched Feynman.ai— an AI science research assistant— with Brandon, which they bootstrapped to **300 signups within a month** of launch.\n\n# **😯 The Problem**\n\n* **Quantum computers** will **revolutionize drug discovery** and **material development** as we will, for the first time, be able to accurately **simulate nature at its most fundamental level**.\n* Leveraging the **trillion-dollar semiconductor** industry, silicon chips offer a **scalable architecture** for building quantum computers.\n\n→ Currently, quantum engineers **spend days, sometimes weeks,** manually configuring silicon chips to **create a single quantum bit (qubit)**, analogous to a bit in a classical computer.\n\n**→ We need millions, if not billions, of qubits** to make a **useful quantum computer.**\n\nAutomation software to create qubits at scale is vital to realize this goal.\n\n# **✅ Our Solution - AI software to create qubits**\n\n* We are building **leading AI software** that creates qubits by **learning and understanding the principles of quantum transport** in semiconductor chips.\n* Our AI software will **replace the human** in the loop, **unlocking rapid qubit generation** and **fabrication feedback iteration cycles**.\n* Automatic qubit creation and control are the foundation of **the first quantum operating system** on **semiconductor chips**.\n\n[Our AI Playground](https://youtu.be/FBeTFudh-Jc)\n\n# **🤝 How You Can Help**\n\n* Sign up for our [**waitlist**](https://www.conductorquantum.com) (Announcements soon!)\n* Quantum engineers who want to get back to building and save themselves 100s of hours per qubit created - Email us at [founders@conductorquantum.com](mailto:founders@conductorquantum.com)\n* We’d love intros to:\n * Chip designers/verifiers/manufacturers\n * Anyone who wants to **bring chip manufacturing back to the USA**", "url": "https://www.ycombinator.com/launches/Lfe-conductor-quantum-quantum-computers-on-silicon-chips-using-ai", "votes": 100, "created_at": "2024-08-22T17:05:04.031Z" } ] }, { "id": 29777, "name": "Zettascale Computing", "slug": "zettascale-computing", "former_names": [ "Exa Labs", "Exa Laboratories", "Zettascale" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/dc824cdcd1866f181c1cae19f0dfc1371a717e51.png", "website": "https://zscc.ai", "all_locations": "San Francisco, CA, USA", "long_description": "AI silicon for the era of recursive self-improvement and superintelligence", "one_liner": "Chips for frontier AI", "team_size": 2, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1722631140, "tags": [ "Hard Tech", "Semiconductors", "Infrastructure", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Summer 2024", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/zettascale-computing", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2024/zettascale-computing.json", "year_founded": 2024, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/zettascale-computing-corp", "x_url": "https://x.com/zettascale", "fb_url": null, "cb_url": null, "github_url": "https://github.com/thezettascale", "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/dc824cdcd1866f181c1cae19f0dfc1371a717e51.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Tom Blomfield", "url": "https://www.ycombinator.com/people/tom-blomfield" }, "founders": [ { "user_id": 779644, "full_name": "Elias Almqvist", "title": "Founder/CEO", "founder_bio": "Founder/CEO of Zettascale Computing, autodidact dropout", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/almqv", "x_url": "https://x.com/fcvprzhfgsybj", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/a6432e5966767866a5568fae25b979f0f8da9f7d.jpg" } ], "jobs": [ { "id": 109821, "title": "Founding Silicon Engineer", "url": "https://www.ycombinator.com/companies/zettascale-computing/jobs/E3xe53H-founding-silicon-engineer", "location": "San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Hardware", "salary_range": "$200K - $300K", "equity_range": "1.00% - 2.00%", "experience": "1+ years", "visa": "Will sponsor", "skills": [ "Tcl", "Verilog", "FPGAs" ] } ], "news": [ { "title": "9 startups that stood out on YC Demo Day 2 | TechCrunch", "url": "https://techcrunch.com/2024/09/26/9-startups-that-stood-out-on-yc-demo-day-2/", "date": "Sep 26, 2024" } ], "launches": [ { "id": 120562, "title": "XPU Grasshopper: An AI chip designed for the era of recursive self-improvement", "tagline": "AI chip co-designed with AI for the era of recursive self-improvement", "body": "![uploaded image](/media/?type=post&id=120562&key=user_uploads/779644/45160b6c-c87e-4ed1-ad59-7ded469a382d)\n\nToday we’re announcing XPU Grasshopper, our AI architecture co-designed with AI!\n\nIt went from its first tokens to 816x faster in 13 weeks on FPGA.\n\nWith a very small team and autonomous AI agents, we were able to design the hardware and software together. The agents rewrote kernels, reworked the hardware overlay, and ran and tested their own FPGA builds.\n\nRunning gemma-3-1b-it (yes, it runs other models too, but that’s for the next launch :)) at more than 51 tok/s and over 90% utilization at batch 1, on four tiles on an FPGA, measured end to end, to prove out our micro-architecture and software stack before silicon.\n\nWe wrote up the full story, including the day-by-day optimizations the agents found, the Mutation Tile Unit architecture, and the benchmarks: \n\n100 numbered FPGA devkits are open for pre-order, with early cluster API and SSH access: \n\nRead more: ", "url": "https://www.ycombinator.com/launches/VMY-xpu-grasshopper-an-ai-chip-designed-for-the-era-of-recursive-self-improvement", "votes": 7, "created_at": "2026-10-07T16:33:31.723Z" }, { "id": 83472, "title": "Exa Laboratories - 27.6x more efficient chips for AI 🔥🚀", "tagline": "Reconfigurable chips for AI that are 27.6x more energy efficient.", "body": "### TL;DR:\n\nWe're building reconfigurable chips for AI that are up to 27.6x more efficient and powerful than the H100 GPUs. This could save data centers hundreds of millions to billions in annual energy costs.\n\n### Meet the Team\n\nHello! We're [Elias](https://www.linkedin.com/in/almqv/) and [Prithvi](https://www.linkedin.com/in/prithvi-raj-eng/) from [Exa](https://exalaboratories.com/). We're developing **reconfigurable chips for AI** that are up to around **27\\.6x\\* more efficient and performant** than the modern H100 GPUs.\n\n\\*: [_Read our litepaper!_](https://exalaboratories.com/litepaper)\n\n![uploaded image](/media/?type=post&id=83472&key=user_uploads/779644/fe720272-a21f-4761-a766-9b90dc6401a9)\n\n[**CEO, Elias Almqvist**](https://www.linkedin.com/in/almqv/) (right): Self-taught engineer who also studied computer science and computer engineering (dropped out and founded Exa, btw) at Chalmers University of Technology. Previously worked in the embedded software space but also worked on various aerospace projects at university.\n\n[**CTO, Prithvi Raj**](https://www.linkedin.com/in/prithvi-raj-eng/) (left): Holds an MEng from the world-leading Computational Stats & ML Lab at Cambridge. During his time there, he fell in love with scientific machine learning, a field that demands bespoke neural network architectures and extreme hardware efficiency, and also interned at Microsoft as a software engineer.\n\n### The problems!\n\nThe AI industry faces critical challenges threatening its sustainable growth:\n\n1. **Unsustainable Energy Consumption**: Modern GPUs consume 600-1000 W per unit, creating massive scaling issues for data centers. Large data centers face energy costs in the hundreds of millions to potentially billions each year. **GPU power draw seems to be increasing with each new release**, while **compute per area has remained the same** for the past 5 years.\n2. **Exponential Compute Demand**: With AI advancements, computational power demand is rapidly increasing. Unchecked, this trend could lead to an energy crisis, impeding AI progress and costing data centers billions of dollars.\n3. **Hardware Limitations**: **Current fixed architectures constrain AI innovation**. They lack the versatility to efficiently support diverse AI architectures and custom neural network designs crucial for solving real-world problems.\n\n### The solution.\n\nExa's polymorphic computing technology addresses these challenges:\n\n* **Reconfigures for each AI model architecture**, maximizing efficiency and versatility\n* Supports diverse approaches, from **transformers** and **GPTs** to novel AI architectures (e.g., the new [**Kolmogorv-Arnold Networks (KAN)**](https://arxiv.org/abs/2404.19756))\n* Early simulations indicate potential efficiency gains of up to **27\\.6x** over the H100 GPUs\n\n**This technology could save data centers hundreds of millions to billions in annual energy costs**, significantly reducing operational expenses and environmental impact.\n\n![uploaded image](/media/?type=post&id=83472&key=user_uploads/779644/12f4a895-8885-4089-a331-920fb65b683c)\n\nFor a somewhat deeper technical dive, refer to our [litepaper](https://exalaboratories.com/litepaper)!\n\n### Asks :)\n\n* Read our [litepaper](https://exalaboratories.com/litepaper)! All feedback welcome!\n* Introduce us to anyone in the scientific machine learning space and/or someone conducting research in AI, **particularly those who have very “_cursed model architectures.”_**\n* Get us in contact with any data center, AI research organization, or GPU cloud provider (i.e., AWS, OpenAI, Anthropic, DeepMind, Lambda).\n* Give us intros to semiconductor industry professionals, particularly those interested in **bringing back chip manufacturing to the US**!\n\nFeel free to reach us at [founders@exalaboratories.com](mailto:founders@exalaboratories.com), **we would love to hear your feedback and answer your questions!**", "url": "https://www.ycombinator.com/launches/LiK-exa-laboratories-27-6x-more-efficient-chips-for-ai", "votes": 35, "created_at": "2024-08-27T19:36:23.464Z" } ] }, { "id": 30233, "name": "Inversion Semiconductor", "slug": "inversion-semiconductor", "former_names": [ "Axiom Semiconductor Inc.", "Axiom Semiconductor" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/f8f65cc20ede5375e5fb2b79c8dcf6d37b04f4c2.png", "website": "https://www.inversionsemi.com", "all_locations": "San Francisco, CA, USA", "long_description": "Inversion Semiconductor is developing the next-generation chip fabrication machine, to create the most powerful chips 15x faster. Our vision is to reshore advanced chip fabrication capabilities in the West.\r\n\r\nWe're building a lithography machine. Lithography uses light to pattern circuit features on silicon. We're scaling transistors to their physical limits by shrinking particle accelerators 1000x, to create a high power light source. \r\n\r\nUsing our light source we will double transistor density for a given numerical aperture and 3x throughput.", "one_liner": "Manufacturing the most powerful chips, 15x faster", "team_size": 9, "industry": "Industrials", "subindustry": "Industrials -> Manufacturing and Robotics", "launched_at": 1740019402, "tags": [ "Hardware", "Manufacturing", "Semiconductors" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Winter 2025", "status": "Active", "industries": [ "Industrials", "Manufacturing and Robotics" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/inversion-semiconductor", "api": "https://devasheeshg.github.io/yc-api/batches/winter-2025/inversion-semiconductor.json", "year_founded": 2024, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/inversion-semiconductor/", "x_url": "https://x.com/inversionsemi", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/f8f65cc20ede5375e5fb2b79c8dcf6d37b04f4c2.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Aaron Epstein", "url": "https://www.ycombinator.com/people/aaron-epstein" }, "founders": [ { "user_id": 1787486, "full_name": "Rohan Karthik", "title": "Founder/CEO", "founder_bio": "Co-founder & CEO of Inversion Semiconductor (W25), developing next-gen semiconductor lithography machines. \nMasters in Mechanical Engineering from Imperial College London & Royal Academy of Engineering awardee. \nPreviously automated chip design at Arm and led the Karman Space Programme to build record-breaking high power rockets. ", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/rohan-karthik-60a0b61b7/", "x_url": "https://x.com/rohankarthik_?s=11&t=VBdqSXL_9iUGm2d8V2oKBg", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/640f0673236b8d2a684219c698df989fd02754dc.jpg" }, { "user_id": 2326493, "full_name": "Daniel Vega", "title": "Founder/CTO", "founder_bio": "Co-founder & CTO of Inversion Semiconductor (W25), developing next-gen lithography machines. \nMasters in Applied Physics from University College London, with a focus on applications of particle physics. \nPreviously created novel ML models for stability optimization of tabletop particle accelerators at CERN, and developed particle accelerators for cancer treatment at Lumitron Technologies\n", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/daniel-r-vega/", "x_url": "https://twitter.com/daniel_r_vega", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/95a252674e588a5c32406c68d263bbce51435bf5.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 87848, "title": "Inversion Semiconductor – Scaling Chips to their Physical Limits", "tagline": "Manufacturing the most powerful chips 15x faster", "body": "# Scaling Chips to their Physical Limits\n\nImagine a chip fabrication machine that produces the most powerful chips 15x faster.\n\nSeven months ago, Rohan was automating chip design at Arm while finishing his master’s in Mechanical Engineering at Imperial College London. Meanwhile, Daniel was creating novel ML models for stability optimization of tabletop particle accelerators at CERN. All while completing his master’s in Applied Physics at University College London.\n\nWe realized that we could build a novel lithography machine, to truly kill Moore’s Law. And we could do this by shrinking particle accelerators 1000x, to build a high power light source driven by laser wakefield acceleration (LWFA). \n\nHere’s a concept video of how our lithography machine will work:\n\n\n\n# Background\n\nLithography is the process of using light to pattern circuit features on silicon. It’s the most important step in making chips. \n\nWith a monopoly on advanced lithography machines, ASML produces 13.5 nm “EUV” light by blasting tin droplets and directing the light on to a wafer using mirrors. However, advanced chips constantly demand finer circuit features. To improve resolution, ASML enlarges its mirrors, a trade-off that significantly increases system complexity and cost.\n\nOver the next decade ASML targets 1 kW of EUV light out, with 1 MW of power in. We aim to achieve 10 kW of even shorter-wavelength light. This will also enable our light source to power multiple lithography machines, unlocking billions in annual revenue gains for fabs.\n\n# Currently\n\nWe aim to generate the required high power light using “tabletop” particle accelerators capable of accelerating electrons to extremely high energies over centimeters, rather than the kilometers needed for large accelerators at CERN and SLAC. We’ll do this using plasma waves (wakefields) driven by a high power laser. \n\nSo far we have:\n\n* Set-up a mini laser lab in the basement of the YC office, to test our novel laser stability algorithms\n* Developed initial LWFA prototypes to generate small-wavelength light.\n\nWe’ve secured a strategic partnership with the world’s leading research group for LWFA development – Lawrence Berkeley National Lab and the Berkeley Laser Lab Accelerator (BELLA). Our collaboration, dubbed the Laser Undulator eXperiment (LUX) or BELLA-LUX (Beautiful Light), is initially focused on improving laser stability and testing light generation using our prototypes.\n\n![uploaded image](/media/?type=post&id=87848&key=user_uploads/1787486/4977528a-59c0-47a9-944f-0cf3211ffa2c)\n\n![uploaded image](/media/?type=post&id=87848&key=user_uploads/1787486/757f3d74-9e83-4864-bd8b-6d105de5d7a5)\n\n# Next Steps\n\nDuring the BELLA-LUX collaboration, we aim to build a high power, tunable light source – STARLIGHT. We are currently exploring early applications to accelerate technical development towards lithography. Companies like Tesla and Applied Materials are interested in potential applications for industrial x-ray imaging and semiconductor mask inspection.\n\nOur goal is to generate 1 kW of soft x-ray light (20nm – 6 nm). If successful, this milestone will pave the way for a user facility, where booking beam time will be as simple as reserving a SpaceX launch—using your credit card. \n\nSimultaneously, we will develop novel mirror systems to reflect and focus generated x-ray light. This will allow us to demonstrate silicon patterning with our initial LITH-0 system, powered by STARLIGHT.\n\n# Asks\n\nIf you know incredible plasma / particle accelerator scientists or lithography engineers, we’d love an introduction.\n\nIntros to VPs / C-Suite at semiconductor manufacturing companies\n\nGot spare laser system parts (optics, gratings, actuators etc)? We’ll take them.\n\n[Lab snacks](https://neil.computer/notes/thorlabs-lab-snacks/)\n\n![uploaded image](/media/?type=post&id=87848&key=user_uploads/1787486/f67b95de-7fd7-46e5-9b82-f26ad0b04ade)\n\n![uploaded image](/media/?type=post&id=87848&key=user_uploads/1787486/11a71540-2837-40cd-a44d-937e09753418)\n\n", "url": "https://www.ycombinator.com/launches/Mqu-inversion-semiconductor-scaling-chips-to-their-physical-limits", "votes": 54, "created_at": "2025-02-20T03:24:56.576Z" } ] }, { "id": 31182, "name": "Visibl Semiconductors", "slug": "visibl-semiconductors", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/c9acdb09765b62086883672feeb576e191249bff.png", "website": "https://visiblsemi.com", "all_locations": "San Francisco, CA, USA", "long_description": "Visibl Semiconductors makes custom silicon accessible to hardware companies, starting with power electronics. We are an AI-native custom-silicon design partner that cuts ASIC development cost and timeline on mature nodes, helping teams deliver better performance and lower BOM cost.\r\n\r\nWe work with data-center and AI-infrastructure power, motor drives, industrial automation and robotics, industrial power supplies and conversion, battery systems and e-mobility powertrains, EV charging, solar, energy storage, grid power, HVAC, heat pumps, and appliances.\r\n\r\nV1 boards built from off-the-shelf parts are great for getting to market quickly, but scaling to v2+ volume requires optimizing cost, size, and manufacturability. Visibl folds those parts into custom silicon built around the product: a simpler BOM, reclaimed board space, fewer supply constraints, and automation-ready assembly.\r\n\r\nWe manage the full path from architecture and design through verification, fabrication, packaging, and production-ready silicon, working alongside hardware teams so they do not need an in-house chip team.", "one_liner": "Custom silicon for power electronics", "team_size": 3, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1767637338, "tags": [ "Hard Tech", "Enterprise", "Enterprise Software", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Winter 2026", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/visibl-semiconductors", "api": "https://devasheeshg.github.io/yc-api/batches/winter-2026/visibl-semiconductors.json", "year_founded": 2024, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/visiblsemi/", "x_url": "https://x.com/visiblsemi", "fb_url": null, "cb_url": "https://www.crunchbase.com/organization/visibl-semiconductors", "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/c9acdb09765b62086883672feeb576e191249bff.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Tyler Bosmeny", "url": "https://www.ycombinator.com/people/tyler-bosmeny" }, "founders": [ { "user_id": 931842, "full_name": "Bryce Neil", "title": "Founder/CEO", "founder_bio": "Co-founder & CEO at Visibl Semiconductors. Passionate technologist and recipient of two of Canada’s most competitive academic scholarships. Bryce is a computer engineer with experience across engineering, data, and business. He has built production software and data systems for Deloitte’s OmniaAI team, healthcare, and the public sector. His work has run in leading U.S. hospitals and supported teams globally.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/bryceneil/", "x_url": "https://x.com/BryceNeil__", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/f4a73099532b0428b2822b3d566c3aa58aa1a33e.jpg" }, { "user_id": 2574530, "full_name": "Jordon Kashanchi", "title": "Founder/CTO", "founder_bio": "Co-founder & CTO of Visibl Semiconductors. Jordon previously worked at Microsoft, Arm, and Intel, building expertise in AI accelerators, autonomous vehicle hardware, and graphics. Most recently at Microsoft, he designed digital logic and microarchitecture for next-gen custom AI silicon. He holds an MS in ECE from UT Austin and is published in PNAS and ACM.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/jordon-kashanchi-46357b143/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/8c29f07f5f652b30a9a450937d9ee7519a73abfa.jpg" } ], "jobs": [ { "id": 113109, "title": "Senior Digital IC Engineer — RTL Design & Verification", "url": "https://www.ycombinator.com/companies/visibl-semiconductors/jobs/o2iGDo7-senior-digital-ic-engineer-rtl-design-verification", "location": "Remote (US)", "type": "Contract", "role": "Engineering", "role_type": "Hardware", "salary_range": "$180K - $250K", "equity_range": "", "experience": "6+ years", "visa": "US citizen/visa only", "skills": [ "Verilog", "FPGAs" ] } ], "news": [], "launches": [ { "id": 97968, "title": "Visibl Semiconductors: The First AI-Enabled Coordination Layer for Chip Design", "tagline": "Meet Visibl, The First AI-enabled Coordination Layer for Chip Design", "body": "Hey everyone 👋\\\nWe’re Bryce and Jordon, co-founders of VISIBL SEMICONDUCTORS™\\\n\\\n**Launch video:** \n\n---\n\n**TL;DR**\\\n_Visibl is the first coordination layer for chip design._ Requirements, architectural intent, and implementation drift out of sync as designs and teams scale. Visibl surfaces drift early, opens cases with evidence, and delivers review-ready fixes enabling improved schedule, cost, and risk outcomes in chip design.\n\nCheck out LinkedIn post here:\\\n\n\n**Problem**\\\nCoordination has always been a human job: monitoring drift, triaging failures, keeping the schedule aligned. It demands constant vigilance, reacting to failures, proactively scanning for issues, always watching.\n\nAs designs scale, no one can hold all that context: the specs, the implementation, the test results, the decisions scattered across Slack, Jira, and docs. Issues slip through. Drift compounds. We saw this firsthand. There was no software to solve it. So we're building it.\n\nOur experience spans chip design and high-stakes production systems. We're solving a problem there was never enough human bandwidth to address, but one that directly impacts the most important outcomes in chip design: schedule, cost, and risk.\n\n**What Visibl Does**\\\n\\\n**Monitors** - specs, implementation, CI, and all design collateral to detect drift early\n\n**Investigates** - creates cases with evidence: spec sections, RTL refs, CI logs, historical decisions\n\n**Proposes** - agents suggest fixes, run verification, package review-ready diffs\n\n**Gates** - human approval required, nothing ships without explicit sign-off\n\n### —\n\n\\\n**Results**\\\n\\\n**Schedule** - Eliminate weeks lost waiting for the one engineer with context to debug failures\n\n**Cost** - 10x less engineering overhead on triage; your team builds instead of firefighting\n\n**Risk** - Catch issues early to minimize rework; avoid late-stage surprises that lead to $10M+ respins\\\n\\\n\\\n\\\n\\\n**Instant Dispatch & Case Creation**\n\n![uploaded image](/media/?type=post&id=97968&key=user_uploads/931842/d732540d-c0f2-416d-9402-378b41735ffe)\n\nAgents spin up immediately on regressions, failing PR checks, spec updates, and more. Visibl opens a case automatically.\n\n---\n\n# \n\n—\n\n\\\n**Evidence Bundle**\n\n![uploaded image](/media/?type=post&id=97968&key=user_uploads/931842/e869a320-410e-4c42-9126-535bd4c9b4be)\n\n\\\nEach case comes preloaded with spec sections, RTL refs, CI logs, and decision history.\n\n# \n\n—\n\n\\\n**Recommended Fix**\n\n![uploaded image](/media/?type=post&id=97968&key=user_uploads/931842/d5e63a58-2b58-4e78-8278-652a0808b651)\n\nVisibl proposes three fix paths and recommends the best one for approval. User can also clarify and specify their own intent.\n\n# \n\n—\n\n\\\n**Verified Review-Ready Diff**\n\n![uploaded image](/media/?type=post&id=97968&key=user_uploads/931842/45650b40-9fc2-477a-8ffa-8c29cf6bac09)\n\nApproved changes are applied, verified, and packaged as a review-ready diff with results.\\\n\\\n\\\n\\\n**Role-Based, Team-Based, and Individual Views**\n\n![uploaded image](/media/?type=post&id=97968&key=user_uploads/931842/2c568efd-b5a0-42db-be95-97f9cbfde4d8)\n\nRole-specific views surface the same underlying truth at the right level of detail. For example, the executive view shows how Visibl ambiently ingests signals across the org and distills them into what leaders care about most—readiness, schedule impact, and top tapeout risks—so they can take action quickly. **Visibl also lets executives (and every role) act directly on these insights, drill into the underlying evidence, assign owners, and drive cases to resolution.**\n\n\\\n**Our Ask**\\\n\\\n**If you have a friend who designs chips at a semiconductor or hardware company, we would really appreciate an intro.** Even a quick forward of this post helps.\\\n\\\nIf you are a:\n\n* _DV / CI owner_\n* _Design methodology / flow owner_\n* _Team heading into integration, freeze, or pre-tapeout_\n\n…we’d love to talk.\n\n**Schedule a demo:** [**founders@visiblsemi.com**](mailto:founders@visiblsemi.com)\n\n---", "url": "https://www.ycombinator.com/launches/PU8-visibl-semiconductors-the-first-ai-enabled-coordination-layer-for-chip-design", "votes": 13, "created_at": "2026-02-19T15:43:41.410Z" } ] }, { "id": 31277, "name": "Dipole Labs", "slug": "dipole-labs", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/b476fcfad147bfb48b55b119e09431103b41f4d8.png", "website": "https://dipolelabs.com/", "all_locations": "Boston, MA, USA", "long_description": "", "one_liner": "AI-controlled optical switching for AI clusters", "team_size": 0, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1786560399, "tags": [ "Hard Tech", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/dipole-labs", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/dipole-labs.json", "year_founded": 2026, "city": "Boston", "country": "US", "linkedin_url": "", "x_url": "", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/b476fcfad147bfb48b55b119e09431103b41f4d8.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Jared Friedman", "url": "https://www.ycombinator.com/people/jared-friedman" }, "founders": [ { "user_id": 3178902, "full_name": "Deepankur Thureja", "title": "Founder/CEO", "founder_bio": "CEO & Co-founder @ Dipole Labs\n\nBuilding optical switching and compute modules that make AI clusters faster and more energy efficient.\n\nPreviously I was a postdoctoral researcher at Harvard where I developed advanced photonic and quantum devices, working at the intersection of materials science, optics, and AI.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/dthureja", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/ec3f292a37bbde4475aa4c89de8203153d747800.jpg" }, { "user_id": 3179632, "full_name": "Gabriele Pasquale", "title": "Founder/CTO", "founder_bio": "Co-Founder & CTO @ Dipole Labs\n\nBuilding optical switching and compute modules that make AI clusters faster and more energy-efficient.\n\nPreviously, I was a postdoctoral researcher at Harvard, where I developed advanced photonic and quantum devices, working at the intersection of materials science, optics, and AI.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/gabrielepasquale", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/4ab80d1378669d55ada2deb72073e9390f4cbbae.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 110374, "title": "Dipole Labs: Shooting lasers to solve the billion-dollar bottleneck inside AI datacenters", "tagline": "High-speed optical circuit switches that keep data moving as light, giving AI clusters up to 25% more useful compute from the same hardware.", "body": "**The most expensive computers ever built spend about half their time waiting for data.** As AI clusters scale, it's increasingly the network that limits how much compute you can actually use.\n\n**What we're building** Dipole Labs builds high-speed optical circuit switches for AI data centers. Between racks, data already travels as light, but routing it usually means converting it to electricity and back, burning power, generating heat, and adding latency. Dipole's switch keeps data in the optical domain, targeting sub-microsecond reconfiguration at large port counts, so the network can reshape itself around each workload.\n\nAn AI-native control layer learns GPU communication patterns and synchronizes optical reconfiguration with training and inference, turning the network into an active accelerator instead of a bottleneck.\n\n**Why it matters** The result: a 10,000-GPU cluster could perform like one with 12,500 GPUs, up to 25% more useful compute from the same hardware. At the scale of a 1 GW data center, that's up to $1 billion in additional compute capacity every year. Optical switching is just the start, the same platform extends from moving data as light to computing with it.\n\n**Who we are** Deepankur and Gabriele met as postdocs at Harvard and have spent the last decade building the photonic expertise behind this technology. Deepankur (CEO) built scalable quantum-optical hardware at ETH Zurich, published in Nature, and was awarded the ETH Medal for his doctoral thesis. Gabriele (CTO) has built nanophotonic and quantum devices at EPFL, and solved a decade-old condensed-matter physics problem published in Nature Materials, which earned the IBM prize from the Swiss and Austrian Physical Society.\n\n**Our ask** We're opening design partnerships with hyperscalers and neoclouds that want more useful compute from the hardware they already run, plus collaborations with photonic foundries to take our custom devices from prototype to scale. If that's you, let's talk.", "url": "https://www.ycombinator.com/launches/SiE-dipole-labs-shooting-lasers-to-solve-the-billion-dollar-bottleneck-inside-ai-datacenters", "votes": 9, "created_at": "2026-08-13T17:30:00.146Z" } ] }, { "id": 31362, "name": "Discovered Materials", "slug": "discovered-materials", "former_names": [ "MatForge", "Matforge", "matforge" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/8369f21b7293d92e30b956a07f47bda16f550d10.png", "website": "https://discoveredmaterials.com", "all_locations": "San Francisco, CA, USA", "long_description": "We use AI to discover new materials for the semiconductor industry - specifically datacenters and fabs. Finding novel materials today takes 10+ years of lab work. We aim to compress that timeline to months, using a swarm of AI agents.\r\n\r\nAkash completed his PhD at Stanford on material discovery for semiconductors. The materials he discovered for nanoscale interconnects have been adopted into the roadmaps of Intel and TSMC. Advaith was the founding applied scientist at Persona AI (acquired by Luma Labs), where he built long horizon autonomous agents for major telecom and crypto companies.\r\n\r\nPower consumption and heat release from AI chips is doubling every year. The semiconductor industry needs new materials to keep this exponential going - Discovered Materials will help find them. ", "one_liner": "AI scientists to discover materials for the semiconductor industry.", "team_size": 2, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1773874719, "tags": [ "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Spring 2026", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/discovered-materials", "api": "https://devasheeshg.github.io/yc-api/batches/spring-2026/discovered-materials.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/discoveredmaterials/", "x_url": "https://x.com/discoveredmat", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/8369f21b7293d92e30b956a07f47bda16f550d10.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Aaron Epstein", "url": "https://www.ycombinator.com/people/aaron-epstein" }, "founders": [ { "user_id": 1591131, "full_name": "Advaith Sridhar", "title": "Founder/CTO", "founder_bio": "Founder at Discovered Materials. Alma Matter: CMU, IIT-Madras", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/advaith-sridhar/", "x_url": "https://x.com/advaith_sridhar", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/a2a4eab0b5bf3bce54ab8ffd698f21f9a70b5b01.jpg" }, { "user_id": 3366857, "full_name": "Akash Ramdas", "title": "Co-Founder", "founder_bio": "Discovering the next silicon using AI scientists. Co-founder at Discovered Materials\nMS, PhD, Post-Doc at Stanford - Material Science and Engineering", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/akashramdas/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/a6951fc1e2371c91e2a13ef33d4a33fbfe2947fb.jpg" } ], "jobs": [ { "id": 103669, "title": "Founding Equipment Engineer", "url": "https://www.ycombinator.com/companies/discovered-materials/jobs/0mX5dLu-founding-equipment-engineer", "location": "Mountain View, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Chemical engineering", "salary_range": "$150K - $250K", "equity_range": "1.00% - 2.00%", "experience": "1+ years", "visa": "Will sponsor", "skills": [] } ], "news": [], "launches": [ { "id": 99882, "title": "Matforge - AI Scientists to discover new semiconductor materials", "tagline": "Discovering 10x better materials for use in next generation electronic chips", "body": "# Accelerating scientific discovery\n\n**Tl:dr** We’re building AI scientists to discover new materials for the semiconductor industry. If you know **Packaging/thermal engineers** at chip companies like NVIDIA, AMD, Groq, Cerebras, Google, Intel, Samsung, TSMC etc, please put us in touch! \n\n—----------\n\nDiscovering a material with commercial viability is usually a story of persistence.\n\nThe incandescent lightbulb filament came not from a single guess, but from Edison trying **6000+** candidate materials over 20 years. The first transistor ever made in Bell labs was famously **not with silicon**, but germanium.\n\n![uploaded image](/media/?type=post&id=99882&key=user_uploads/3366857/c84e2115-5738-4845-a320-4825fc7ae0c8)\n\n_(left) The first transistor, made from Germanium. (right) some materials Edison tried as lightbulb filaments_\n\nThe same holds true in the semiconductor industry. We really need better materials for our chips, but finding them takes 10+ years of lab work.\n\nAt Matforge, we build AI agents to **accelerate** this process of finding new materials for the semiconductor industry. Our agents work across the entire materials discovery process - coming up with new candidates, synthesizing them and testing them in **physical labs.**\n\n![uploaded image](/media/?type=post&id=99882&key=user_uploads/3366857/fa73a824-db61-4271-8160-39c58b55b6d3)\n\n**The founders -** Advaith has a Masters in AI from **Carnegie Mellon**, and was most recently a **research engineer** at Luma Labs, building agent harnesses and working on frontier models. Akash has a Masters, PhD and PostDoc from **Stanford University** in **materials discovery** for the semiconductor industry. We’ve known each for the last **11 years**, and have even written a book together!\n\nBreakthrough materials will still take many, many experiments. But for the first time, a small team might just have the tools to speed up this search and win.", "url": "https://www.ycombinator.com/launches/Pz0-matforge-ai-scientists-to-discover-new-semiconductor-materials", "votes": 25, "created_at": "2026-04-21T16:04:21.392Z" } ] }, { "id": 32257, "name": "Spectre Intelligence", "slug": "spectre-intelligence", "former_names": [ "Spectre Capital" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/dd275e68bdab3f73081986be229ec8d9f1423ae5.png", "website": "https://www.spectreintelligence.ai", "all_locations": "San Francisco, CA, USA", "long_description": "Spectre Intelligence is a neotrading firm. We create AI traders instead of hiring human ones. Currently trading semis + bio.", "one_liner": "We are a multi-strategy trading firm that trains AI traders. ", "team_size": 2, "industry": "Fintech", "subindustry": "Fintech -> Asset Management", "launched_at": 1787421048, "tags": [ "Biotech", "Investing", "Trading", "Semiconductors" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "Fintech", "Asset Management" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/spectre-intelligence", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/spectre-intelligence.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://linkedin.com/company/spectre-intelligence-ai", "x_url": "https://x.com/spectreintellig", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/dd275e68bdab3f73081986be229ec8d9f1423ae5.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Ankit Gupta", "url": "https://www.ycombinator.com/people/ankit-gupta" }, "founders": [ { "user_id": 1251785, "full_name": "Michelle Li", "title": "Founder/CEO", "founder_bio": "Co-founder and CEO at Spectre Intelligence, on leave from Harvard (I studied Economics & Biology and was originally class of '27). Previous research across generative protein language models, bacteriophages, CRISPR Cas9, and more. ISEF grand award winner, RSI and STS scholar.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/michelle-zhiya-li/", "x_url": "https://x.com/michellezli", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/6eacc1c85541c9e6f7a907d66e8c4b4d53136b3b.jpg" }, { "user_id": 2574740, "full_name": "Joshua Zyzak", "title": "Founder/CTO", "founder_bio": "Founder at Spectre Capital, CS and EE at Harvard, researched deep-RL controllers for quadruped robots and multimodal LLM-robotics", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/josh-zyzak/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/3a94186fa13fa1983bac60969d2c2ddafff69b21.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 112001, "title": "Spectre Intelligence - a neotrading firm", "tagline": "We're an AI trading research firm, currently in semiconductors and biotech.", "body": "TL;DR: Spectre Capital is a multi-strategy trading firm run by AI agents, not human analysts. We deploy real capital to capture every decision, reasoning trace, and ground-truth outcome, so our agents learn and compound from every mistake. Most AI trading labs pay egregious amounts for training data. Ours pays us when we win.\n\nWe left Harvard after starting a hedge fund from our college dorm (go Currier!).\n\nNow we’re building Spectre Intelligence, a neotrading firm training superhuman AI traders. \n\n**The problem**\n\nIntelligence is getting cheaper, and it will rewire trading. But the scarcest input to markets isn't compute or data feeds or latency, but rather judgment. That data is fragmented, scarce, and the foundation of entire careers. It is also entirely proprietary and guarded fiercely by firms.\n\n**What we do**\n\nWe collect judgment by trading live. Every position our agents take generates decisions, full reasoning traces, and ground-truth P&L. We think this is the ultimate alignment of incentives in one of the largest TAMs in the world.\n\nThe structure is evolutionary from first principles: open competition inside each pod, and strategies and pods are born and killed constantly. \n\nUnlike a traditional pod shop, spinning up a new pod costs compute, not headcount. Our agents work superhuman hours, monitor a superhuman number of things, and learn from every real and simulated trade. Our AI traders develop specialized strategies in parallel, allowing us to scale far beyond the limits of human bandwidth. This is an edge that scales, compounds, and isn't held by any one employee.\n\n**Traction**\n\n\\- Two live pods: semiconductors and biotech equities. (We picked the verticals, not our AI traders.)\n\n**Why now?**\n\nAI is the worst it will ever be, LLM traders aren't even good yet, but we believe the writing is on the wall and want to be on the frontier. Quant funds were arguably the first agent labs: ML theory embedded for decades, quants as very expensive agents. We're building the generation after.\n\n**The ask**\n\nIf any of this resonates, feel free to reach out: michelle@spectreintelligence.ai\n\nWe’re also collecting an expert network across semis + biotech, so if you have experience, feel free to join at ", "url": "https://www.ycombinator.com/launches/T8T-spectre-intelligence-a-neotrading-firm", "votes": 5, "created_at": "2026-08-24T15:47:00.614Z" } ] }, { "id": 32517, "name": "Standard Machines", "slug": "standard-machines", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/20aa62fc0a930e7bfdba7047f185bab421afd2b2.png", "website": "https://standardmachines.com", "all_locations": "San Francisco, CA, USA", "long_description": "We build environments and evaluations to train and evaluate models on advanced chip design.", "one_liner": "Teaching AI to Design Chips", "team_size": null, "industry": "B2B", "subindustry": "B2B", "launched_at": 1785623138, "tags": [ "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "B2B" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/standard-machines", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/standard-machines.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/standardmachines/", "x_url": "https://x.com/stanmachines", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/20aa62fc0a930e7bfdba7047f185bab421afd2b2.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Ankit Gupta", "url": "https://www.ycombinator.com/people/ankit-gupta" }, "founders": [ { "user_id": 1978488, "full_name": "Jacob Peake", "title": "Founder/CEO", "founder_bio": "Founder at Standard Machines. \nEx GPU Architect at Apple.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/jacob-peake/", "x_url": "https://x.com/jacobpeake", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/1e58da36d411b29af7b6af0bb04427b019ed414f.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 111880, "title": "Standard Machines. Teaching AI to Design Advanced Chips.", "tagline": "Standard Machines builds environments to train and evaluate models on advanced chip design tasks. We work with frontier labs to push their model capabilities.", "body": "**The Idea**\n\nAdvancement in AI relies on chips. Transformers won because they mapped well to GPUs. Frontier Labs are now co-designing their own silicon to maximize intelligence/joule.\n\nIt takes years and 100s of experts to bring a chip from architecture through tape-out.\n\nOur goal as a company is to push the frontier of AI on chip design tasks - enabling advanced chips to be taped-out by small teams in months.\n\nWe also believe this is the path forward to achieving true recursive self-improvement (RSI). Where AI designs better chips and better chips train more intelligent AI.\n\nTo achieve this, we're building **RL Environments For Long-Horizon Chip Design.**\n\nOur environments enable 1000s of parallel rollouts for training on chip design tasks. We also curate a private held-out test set for performing evals in the environment to compare model capabilities.\n\n![uploaded image](/media/?type=post&id=111880&key=user_uploads/1978488/da8f5344-b2f0-4613-b8ef-5ee18a23300c)\n\n---\n\n**What Exists**\n\nChip design should be a perfect domain for this type of RL. Instead:\n\n\\- The academic benchmarks are one-shot puzzles of \\~100 lines, and they're in every training set.\n\n\\- The field's de facto standard (NVIDIA's CVDP) has saturated - going from 34% to 97% once agents could iterate against the grader.\n\n\\- The published tasks are short-horizon and graded by running testbenches. In one study, designs that passed their bundled testbenches 95-97% of the time were only \\~20% correct under formal checking.\n\nAnd none of it resembles the real loop: months of work, tools in the loop, and hard trade-offs between latency, throughput, area, and power.\n\n---\n\n**What We Build**\n\nOur RL Environment is designed for long-horizon chip design tasks.\n\n\\- **Long-horizon.** One episode is the real loop: choose a microarchitecture, write the RTL, simulate, synthesize, check timing and power, revise.\n\n\\- **Reliable grading.** Every task is an executable contract with exact checking. No LLM judge anywhere in the reward path. Correctness is a hard gate: a fast, small, wrong chip earns zero.\n\n\\- **Physics as the yardstick.** Every task ships with a computed speed-of-light bound: the best the physics of the task allows. Scores are reported as a fraction of that bound, so they're comparable across tasks.\n\n\\- **The full trade-off.** Real chips are trade-offs. We record area, power, latency, and throughput as an unreduced vector - labs can scalarize this into a terminal reward for training however they want.\n\n\\- **Deterministic.** Every graded result replays bit-identically on another machine.\n\n---\n\n**Why Now**\n\nChip Design is increasingly something the frontier labs care about. They are all designing their own custom inference chips. Anthropic is already hiring chip-design RL engineers at $500-850k to build these types of environments in-house - and there’s currently no yardstick that hasn’t been saturated.\n\n---\n\n**Who We Are**\n\nI was the first intern & youngest hire into GPU Architecture at Apple, working with industry-leading architects.\n\nI've seen how leading-edge chips get designed end-to-end: what the loop looks like, and how the power/perf/area trade-offs actually get graded.\n\nOur environments run that same loop & formalize that grading.\n\n**Asks**\n\nIf you’re working on RL, post-training, or data at a lab or neolab, or interested in post-training models for chip-design capabilities. Please reach out, [founders@standardmachines.com](https://www.standardmachines.com/launch).\n\n---\n\n---\n\n---\n\nRead our full launch post, [here](https://standardmachines.com/launch).\n\n\\- [Jacob](https://x.com/jacobpeake)", "url": "https://www.ycombinator.com/launches/T6W-standard-machines-teaching-ai-to-design-advanced-chips", "votes": 22, "created_at": "2026-08-24T17:21:03.769Z" } ] }, { "id": 32584, "name": "Aerogen Systems", "slug": "aerogen-systems", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/235b4dc8ef4a94e38d79ce892c9d55184a2b0224.png", "website": "https://www.aerogensystems.com/", "all_locations": "Ann Arbor, MI, USA", "long_description": "We are building the future of chip manufacturing.\r\n\r\nChips are more advanced than ever, and the features inside them keep getting smaller. But the cleanroom infrastructure supporting their manufacture has not scaled at the same pace. Intel, TSMC, Samsung, and others spend billions building and operating massive cleanrooms, only to isolate their most advanced wafers from the surrounding facility as much as possible.\r\n\r\nWe think that architecture is backwards. Instead of making the entire building cleaner, why not make the machinery itself as clean as possible?\r\n\r\nTalos is our proprietary tool-integrated purification system. It sits directly inside semiconductor equipment and continuously destroys airborne molecular contaminants before they reach the wafer. Instead of fighting contamination by constantly flooding tools with ultra-high-purity nitrogen, Talos keeps the environment inside the machine 10–100x cleaner, without the massive purge-gas bill.\r\n\r\nTalos is powerful on its own, but it is also the foundation for a much bigger vision: the Cleanpipe.\r\n\r\nThe Aerogen Systems Cleanpipe is an ultra-clean interconnect infrastructure that protects wafers as they move from machine to machine across the fab. Rather than relying on a billion-dollar cleanroom to protect every cubic foot of factory space, Cleanpipe creates a controlled environment only where cleanliness actually matters: around the wafer.\r\n\r\nTalos cleans the tools. Cleanpipe connects them. Eventually, we delete the cleanroom and build more advanced chips, at greater scale, with radically less infrastructure. With cleanpipes connecting tools, chip fabs can exist anywhere.", "one_liner": "Modernizing Chip Manufacturing Infrastructure", "team_size": 4, "industry": "Industrials", "subindustry": "Industrials", "launched_at": 1786900126, "tags": [ "Hard Tech", "B2B", "Manufacturing", "Semiconductors" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "Industrials" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/aerogen-systems", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/aerogen-systems.json", "year_founded": 2026, "city": "Ann Arbor", "country": "US", "linkedin_url": "https://www.linkedin.com/company/aerogen-systems-company/", "x_url": "https://x.com/AerogenSystems", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/235b4dc8ef4a94e38d79ce892c9d55184a2b0224.png", "app_video_url": null, "dday_video_url": null, "company_photos": [ "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/e2f1aeb38c2211e11ef666f05de7b888fd393137.png" ], "primary_partner": { "name": "Jon Xu", "url": "https://www.ycombinator.com/people/jon-xu" }, "founders": [ { "user_id": 3388722, "full_name": "Noah Vogel", "title": "Founder/CEO", "founder_bio": "Founder & CEO at Aerogen Systems. Previously engineering intern at SpaceX building Starship actuators and at Draper developing advanced mission simulators. BSE Aerospace Engineering from University of Michigan.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/noahvogel/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/5153adbbedb2cd7f09db195d1d63de5e64513dea.jpg" }, { "user_id": 3422652, "full_name": "Colin Lavery", "title": "Founder/CTO", "founder_bio": "Co-founder & CTO of Aerogen Systems. Previously an electrical engineer at H3D, developing 3D gamma ray imaging systems. BSE Space Sciences and Engineering at the University of Michigan.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/colin-lavery-67b7512a3/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/3b3f944b8190b3fbc2ca61bd6963d1d3707c6976.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 111026, "title": "Aerogen Systems: Building Chip Fabs Without Cleanrooms", "tagline": "Redefining the architecture behind chip manufacturing", "body": "Hi YC!\n\nWe’re [Noah](https://www.linkedin.com/in/noahvogel/) and [Colin](https://www.linkedin.com/in/colin-lavery-67b7512a3/), the founders of [Aerogen Systems](https://www.aerogensystems.com/). We’re building the next generation of clean infrastructure for chip manufacturing.\n\n**TL;DR:** Aerogen Systems makes semiconductor tools clean themselves. Talos, our tool-integrated purification system, continuously destroys airborne contaminants around the wafer, creating 10–100x cleaner tool environments while reducing dependence on ultra-high-purity nitrogen. Over time, Talos becomes the foundation for the Cleanpipe, an ultra-clean interconnect network that lets wafers move between tools without depending on the surrounding cleanroom.\n\n\n\n# **The Problem**\n\n**Chip features keep getting smaller, but cleanrooms do not scale with them.**\n\nSemiconductor manufacturers spend billions building enormous cleanroom facilities, then spend even more trying to isolate their most advanced wafers from the environment they just built.\n\nAs features approach the atomic scale, trace airborne contaminants that were once tolerable can create defects, reduce yield, and disrupt some of the most sensitive manufacturing processes on Earth. Yet the industry's answer has largely been more of the same: cleaner facilities, more filtration, and more ultra-high-purity nitrogen flooding sensitive equipment.\n\n**The proof is in the yield numbers.** 2026 reporting puts Intel’s 18A program between roughly 50% and 65% yield as it pushed the node toward high-volume production. With global semiconductor sales projected to reach **$1.5 trillion** in 2026, every percentage point matters. Improvements in yield and manufacturing efficiency can represent tens of billions of dollars in value.\n\n# **The Solution**\n\nAt Aerogen Systems, we think the industry is approaching this problem backwards.\n\n**The whole factory does not need to be a massive cleanroom.** Only the environment immediately surrounding the wafer does.\n\nTalos is our proprietary, tool-integrated purification system. It sits directly inside semiconductor manufacturing equipment and continuously recirculates and purifies the environment around the wafer. Instead of constantly replacing contaminated gas with more ultra-high-purity nitrogen, Talos destroys contaminants at the point of use, offering 10–100x cleaner tool environments while dramatically reducing dependence on purge gas and consumable filtration.\n\n![uploaded image](/media/?type=post&id=111026&key=user_uploads/3388722/a095a4e2-31a2-4307-b8f1-bca417cb27d7)\n\n_1. Rendering of standalone Talos unit._\n\nBut Talos is only part of the vision.\n\nWith tool-integrated purification units as a foundation, we build **the Cleanpipe: ultra-clean interconnect infrastructure** that protects wafers as they move from machine to machine across the fab. Talos cleans the tools. The Cleanpipe connects tools to each other. Together, they delete the cleanroom and all the expenses that come with it.\n\n# **What We’ve Built**\n\nTalos has progressed through multiple generations of hardware development and is protected by patent-pending IP. We’ve validated the core purification architecture and are now working toward tool integrations, pilots, and commercial deployments with semiconductor manufacturers and equipment companies.\n\n![uploaded image](/media/?type=post&id=111026&key=user_uploads/3388722/a8596c2c-c29b-4271-8d92-85672dce0dc1)\n\n_2. Test results showing Talos bringing industry-standard 6N purification levels down to 8N — a 100x improvement in cleanliness._\n\nThe next step is connecting these purified environments together through the Cleanpipe, creating an ultra-clean path around the wafer from tool to tool and ultimately removing the need to maintain the entire fab as one enormous cleanroom.\n\n# **The Team**\n\nAerogen Systems started as a NASA-backed research group at the University of Michigan, where our team developed the underlying purification technology. \n\nWe have spent the last several years designing, testing, patenting, and rebuilding this technology for extreme manufacturing environments.\n\n* Noah, CEO, worked in manufacturing engineering at SpaceX, where he focused on production rate and yield improvement for the Starship program.\n\n\n* Colin, CTO, previously built advanced particle detectors at H3D and led the team through the earliest design cycles of Talos.\n\n![uploaded image](/media/?type=post&id=111026&key=user_uploads/3388722/4db2a255-30a8-44ee-928b-b07425918094)\n\n# **Our Ask**\n\nWe want to meet semiconductor fabs, equipment OEMs, and manufacturing teams interested in pilots, tool integrations, and commercial deployments. If this sounds like you, please reach out to [hi@aerogensystems.com](mailto:hi@aerogensystems.com)!\n\nWe are building toward a world where fabs no longer need billion-dollar cleanrooms to manufacture the world’s most advanced chips.", "url": "https://www.ycombinator.com/launches/Ssk-aerogen-systems-building-chip-fabs-without-cleanrooms", "votes": 17, "created_at": "2026-08-18T21:15:05.234Z" } ] }, { "id": 33054, "name": "Lamb Labs", "slug": "lamb-labs", "former_names": [ "LAMb Intelligence" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/c5ba47505a760393e85b91acdb4b3933cf8df0a7.png", "website": "http://lamb-labs.com", "all_locations": "San Francisco, CA, USA", "long_description": "Lamb Labs is building Model Processing Units (MPUs), custom AI chips that hardcode LLM weights directly into silicon. Rather than adapting general-purpose processors to run AI models, we're rethinking how LLMs are implemented in hardware to make inference dramatically faster and more energy-efficient.\r\n", "one_liner": "Lightning fast chips with hardcoded AI models", "team_size": 0, "industry": "B2B", "subindustry": "B2B", "launched_at": 1785288921, "tags": [ "Hardware", "B2B", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "B2B" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/lamb-labs", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/lamb-labs.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/lamb-labs/", "x_url": "https://x.com/LambLabs", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/c5ba47505a760393e85b91acdb4b3933cf8df0a7.png", "app_video_url": null, "dday_video_url": null, "company_photos": [ "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/59a091ae426afcd919acf389592f0f3391ed83c8.png" ], "primary_partner": { "name": "Tyler Bosmeny", "url": "https://www.ycombinator.com/people/tyler-bosmeny" }, "founders": [ { "user_id": 726152, "full_name": "Niki Kotecha", "title": "Founder/CEO", "founder_bio": "Founder at Lamb Labs. AI PhD at Imperial College London + I-X Scholar. MEng/BA in Engineering from University of Cambridge. Alan Turing Institute Global Fellowship and 160+ citations", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/niki-kotecha/", "x_url": "https://x.com/KotechaNiki", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/9d7169b597815c0e4b02ff12606c162b4c12432b.jpg" }, { "user_id": 3179989, "full_name": "Thomas Lanning", "title": "Founder/CTO", "founder_bio": "Founder at Lamb Labs. Masters in Mathematical and Theoretical Physics from Oxford. Top of his class in undergraduate at Edinburgh University. (Re)discovered the Higgs-boson using ML and CERN data. ", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/thomas-lanning/", "x_url": "", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/aadf202207708e0feff18ade84592a81efb19f2f.jpg" } ], "jobs": [ { "id": 116541, "title": "Founding AI Accelerator Architect (Research & Hardware Co-Design)", "url": "https://www.ycombinator.com/companies/lamb-labs/jobs/QfZbNOf-founding-ai-accelerator-architect-research-hardware-co-design", "location": "London, England, GB", "type": "Full-time", "role": "Engineering", "role_type": "Hardware", "salary_range": "£60 - £160 GBP", "equity_range": "", "experience": "Any (new grads ok)", "visa": "US citizenship/visa not required", "skills": [] }, { "id": 116543, "title": "Founding ASIC Engineer (Architecture & RTL)", "url": "https://www.ycombinator.com/companies/lamb-labs/jobs/cW2pB1O-founding-asic-engineer-architecture-rtl", "location": "London, England, GB", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "£60 - £160 GBP", "equity_range": "", "experience": "1+ years", "visa": "US citizenship/visa not required", "skills": [] } ], "news": [], "launches": [ { "id": 108778, "title": "Lamb Labs: Custom Chips for AI Inference", "tagline": "Co-designed models and silicon: we hardcode the model architecture into chips targeting 20,000+ tokens per second and 63x higher intelligence per watt.", "body": "**Hi Everyone!** \n\n**We’re Niki and Thomas - cofounders of Lamb Labs.**  \n\n**TL;DR: We build custom AI inference chips that run inference at 20,000+ tok/s and 63x higher intelligence per watt than a traditional GPU. Fully local and private by construction, no subscriptions, no API costs.** \n\n**Our mission: the world’s fastest LLM at the lowest power.** \n\n\n\n**Our hot take: AI models are finally getting good enough to hardcode them directly into silicon.** Once you stop treating the chip as a general-purpose GPU and burn a specific model into hardware, inference gets radically faster and cheaper per watt. Most of the industry is still building flexible, general chips. We think that flexibility is exactly what's wasting your energy. So we’re on a mission to reduce the energy footprint of AI. \n\n**The Problem**\n\nAI is taking power on two fronts: concentrating control of data and intelligence, and consuming ever more electricity to grow. That future scares us, so we're building against it.\n\nHere's the technical root of the waste: **GPUs burn most of their energy during inference moving data, not computing.** LLM/VLM inference is memory-bound, fetching a weight from memory costs \\~100–1000x the energy of the arithmetic you do with it. So you underutilize the GPU you paid for: some GPUs only hit 20–40% compute utilization during LLM inference while the rest idles waiting on memory.\n\nCloud hosting adds its own tax: expensive per-token bills, latency you can't control, network dependencies, and your data leaving your control.\n\n**Our Solution**\n\nWe build the model and the chip together. \n\nThe Hardware Layer\n\n* **Custom architecture, RL-tuned.** We built an RL environment that co-designs the chip architecture for a given model, optimizing directly for speed and energy per token.\n* **Aggressive quantization.** Removes complex math, which shrinks the size and cost of the chip.\n* **Weights on-chip.** The model weights live where the compute is overcoming the memory-bandwidth bottleneck\n\n \n\nBecause everything is hardcoded, it's fully local and secure by construction. No connectivity dependency, nothing leaves the device.\n\nThe Software Layer \n\nDesigning the chip led us to solving a fundamental flaw in LLMs so we are now open-sourcing a new model next week, converted from another open source model, to run 2x faster on any hardware. Come back next week for part 2 of our launch to find out more….\n\n**Our Ask**\n\nIf you answer \"yes\" to any of these, we'd love your help:\n\n* **Are you paying for inference in watts, not just dollars?** Neocloud or private DC operators who are power- or hardware-cost-bound rather than demand-bound, talk to us.\n* **Do you need inference where the cloud isn't an option?** Private AI deployments, regulated, air-gapped, sovereign, or bandwidth-starved deployments.\n* **Do you want to deploy the fastest AI models in your stack?** High frequency trading, agentic workflows \n* **Are you stuck on a thermal or battery budget?** Robotics, wearables, consumer AI hardware where a Jetson-class part is over-provisioned and runs too hot.\n* **Can you introduce us to anyone above?** Warm intros are the single most useful thing.\n\nContact us at [contact@lamb-labs.com](mailto:contact@lamb-labs.com)", "url": "https://www.ycombinator.com/launches/SIU-lamb-labs-custom-chips-for-ai-inference", "votes": 64, "created_at": "2026-08-03T04:56:33.889Z" } ] }, { "id": 33573, "name": "hardware intelligence", "slug": "hardware-intelligence", "former_names": [ "Viki", "hi", "Hardware Intelligence" ], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/3c2193e7412febe2e812491e1a73617bb09eb897.png", "website": "https://hardwareintelligence.ai", "all_locations": "San Francisco, CA, USA", "long_description": "Hardware Intelligence makes chip design tools that cut simulation and debugging time by an order of magnitude. When a chip test fails, engineers need a recording of every internal signal - a waveform. We’ve developed WaveZip, which captures waveforms 500x smaller with 200x less overhead, and Wave, which beats frontier models on industry chip debugging benchmarks. We’re Rishov Sarkar (Georgia Tech Ph.D. in chip simulation) and Athreya Anand (ex-Google, M.S. ML/AI), YC S26. https://hardwareintelligence.ai", "one_liner": "AI tools for the chips your AI runs on", "team_size": 2, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1784052551, "tags": [ "Developer Tools", "Hardware", "Enterprise Software", "Semiconductors", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": false, "nonprofit": false, "batch": "Summer 2026", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "United States of America", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/hardware-intelligence", "api": "https://devasheeshg.github.io/yc-api/batches/summer-2026/hardware-intelligence.json", "year_founded": 2026, "city": "San Francisco", "country": "US", "linkedin_url": "https://www.linkedin.com/company/hardwareintelligence/", "x_url": "https://x.com/hwintelligence", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/3c2193e7412febe2e812491e1a73617bb09eb897.png", "app_video_url": null, "dday_video_url": null, "company_photos": [ "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/84867b76e94b5d17051762179fca04132eaaa7be.png", "https://bookface-images.s3.us-west-2.amazonaws.com/attachments/c8cf823528ccb123bf55a70cc8e1a177803988de.png" ], "primary_partner": { "name": "Jon Xu", "url": "https://www.ycombinator.com/people/jon-xu" }, "founders": [ { "user_id": 551607, "full_name": "Athreya Anand", "title": "Founder/CEO", "founder_bio": "Co-founder & CEO of Hardware Intelligence. Athreya was a tech lead at Google where he led AI efforts across orgs from agentic workflow management tools to prediction models for Google Ventures. He has a Master's from Georgia Tech in Machine Learning and A.I., with technical expertise in agentic tools and chip design through his time at Google, AWS Inferentia, and Tesla. ", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/athreyaanand", "x_url": "https://x.com/athreyaanand", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/d015fb0c86a6bdae44f5b5c36e2b3d18f086454a.jpg" }, { "user_id": 2565323, "full_name": "Rishov Sarkar", "title": "Founder/CTO", "founder_bio": "Co-founder & CTO at Hardware Intelligence. Rishov graduated with his PhD in Electrical & Computer Engineering from Georgia Tech with six published first-author/co-first-author conference papers, including one best paper runner-up. He also developed simulators for AMD's AI Engine accelerator and worked on LLVM-based compilation flows at Siemens EDA. He earned his MS and BS in Computer Engineering from Georgia Tech.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/rishovsarkar/", "x_url": "https://twitter.com/ArkaneMoose", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/d7666af58a4a49fbf9b8355cdffcb981f5df6505.jpg" } ], "jobs": [], "news": [], "launches": [ { "id": 107661, "title": "hardware intelligence: AI tools for the chips your AI runs on", "tagline": "Bringing the $20B chip tooling industry into this decade", "body": "---\n\n---\n\n**Update:** We’ve just launched our second tool, WaveZip - a genuine breakthrough method for capturing and storing waveforms. Read more at \n\n---\n\n---\n\n\n\n—\n\nWe’re Athreya and Rishov - the founders of [@hardware intelligence](https://bookface.ycombinator.com/company/33573). We’re here to pick a fight with the $20B industry whose debuggers suck and won’t open until an ancient license server gives it permission.\n\n**TL;DR: Our first product, Wave, is a SOTA waveform debugger that lives completely in the terminal, built for the agentic era.** An agent can jump you to the moment a design breaks, drag in waveforms and manipulate them, trace bad signals to its source and even prove its fix against the simulation - all visual. We allow teams to build better chips in less time.\n\n**The quick ask:** If you or anyone you know builds or verifies chips (ASICs/FPGAs), please email us! We would love to talk :)\n\n\n\n❌ **The Problem**\n\nThe AI boom is a chip boom - more companies and teams than ever are designing silicon. However, the reality is hardware is not software: you can’t patch a chip after it ships. A bug that reaches manufacturing can be a nine-figure mistake. That’s why **companies spend 70% of the entire chip design process just on verification**.\n\nHardware verification engineers run thousands of simulated tests first on their code (simulation) which typically can take **hours to days**. If one of these tests fail, debugging means reading a waveform - a log of every signal, millions of ticks long, hiding the tick where a value went wrong. It’s literally a needle in a haystack… a big haystack. It’s common for these waveform files to be several gigabytes large. **Finding this needle is the single largest activity in verification.**\n\n**The current tools are dinosaurs.** 20-year-old GUIs behind license servers whose seats run six figures a year sold by our favorite incumbents: Synopsys, Cadence, and Siemens. Free tools are even worse.\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/fd100b13-f0dd-45f0-8ee4-395edf96fcae)\n\nYes. This is from 2026.\n\nSoftware engineers got coding agents. Chip engineers got a queue for a license and whatever this is.\n\n👋 **What Wave actually does**\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/a75818b0-b001-466b-9586-705d26deb5f9)\n\nWave is the first of its kind! **A fully terminal-native waveform debugger with a verification agent built in.** Wave opens files before Verdi, the industry-standard viewer, finishes its license check. Let’s do a quick dive!\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/ac7e5c75-8abb-4a6d-881f-a2a9b883a8b3)\n\n**Why the terminal?** Surprisingly, most hardware engineers are terminal power users - typically doing all their coding in Vim. We wanted to meet them where they are and make our product extremely intuitive to use - we even employ Vim bindings across the interface.\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/d4063fbc-2f57-4b5c-a421-bfaa697433d6)\n\n**Ask in plain english.** _Why is a wave x at 12.4us?_ The agent will pull in signals, act on them and trace the root cause. Everything happens in front of your eyes.\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/8f37dd5c-22f0-4271-b665-a096c5dbfbd2)\n\n**Pick your fix and see it.** Wave will propose different approaches with tradeoffs. The definition of “best” in hardware design depends on the use case. Maybe you want to optimize for performance? Maybe for power? Pick the one for you! Wave re-simulates and re-reads the new waveform. See a diff of how the waveform changed and a visual indication of where the fix was implemented.\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/b0875bc9-fb55-4275-8c7e-11f926bc597d)\n\nNow watch it fix a bug end to end with Rishov!\n\n\n\n🙏 **Asks & Offers**\n\nIf you design chips or lead a team, email us! We’d love to work with you and speed up your RTL development.\n\nKnow someone who does? Email us!\n\nJust want to chat about hardware? **EMAIL US!!**\n\n👬 **The Team**\n\nWe met in our freshman dorm at Georgia Tech nearly a decade ago! We became best friends and roommates for all four years of college - after, Athreya went to NYC to work at Google and Rishov stayed to do his PhD. We promised each other that once we’re free, that we’ll go all-in and work on something we’re passionate about together. Turns out, Rishov’s deep PhD thesis on chip simulation and compilers was the perfect spark.\n\nToday we announce our company and are roommates once again ❤️\n\n![uploaded image](/media/?type=post&id=107661&key=user_uploads/551607/eef30a82-c606-494a-a093-3649920c7857)\n\n—\n\nSay hi 👋 [hi@hardwareintelligence.ai](mailto:hi@hardwareintelligence.ai) · [hardwareintelligence.ai](http://hardwareintelligence.ai)\n\n[@Athreya Anand](https://bookface.ycombinator.com/user/551607) · [athreya@hardwareintelligence.ai](mailto:athreya@hardwareintelligence.ai)\n\n[@Rishov Sarkar](https://bookface.ycombinator.com/user/2565323) · [rishov@hardwareintelligence.ai](mailto:rishov@hardwareintelligence.ai)\n\nP.S. Wave is just the start 👀 We got some super cool things coming to close the loop of hardware engineering. ", "url": "https://www.ycombinator.com/launches/S0T-hardware-intelligence-ai-tools-for-the-chips-your-ai-runs-on", "votes": 50, "created_at": "2026-07-27T16:00:24.675Z" } ] }, { "id": 33838, "name": "Simantic", "slug": "simantic", "former_names": [], "small_logo_thumb_url": "https://bookface-images.s3.amazonaws.com/small_logos/12eef74104b6e57636a6f0d2305e3a2d18d5c2e5.png", "website": "https://simantic.com", "all_locations": "Waterloo, ON, Canada", "long_description": "Simantic is modernizing the embedded firmware industry with hardware simulation developed for the adoption of AI in hardware engineering. Simantic gives both humans and AI the visibility into hardware previously limited by the physical world.", "one_liner": "Firmware simulation for AI agents", "team_size": 4, "industry": "B2B", "subindustry": "B2B -> Engineering, Product and Design", "launched_at": 1782327485, "tags": [ "Developer Tools", "Hardware", "Semiconductors", "Electronics", "AI" ], "tags_highlighted": [], "top_company": false, "isHiring": true, "nonprofit": false, "batch": "Fall 2026", "status": "Active", "industries": [ "B2B", "Engineering, Product and Design" ], "regions": [ "Canada", "America / Canada" ], "stage": "Early", "app_video_public": false, "demo_day_video_public": false, "app_answers": null, "question_answers": null, "url": "https://www.ycombinator.com/companies/simantic", "api": "https://devasheeshg.github.io/yc-api/batches/fall-2026/simantic.json", "year_founded": 2025, "city": "Waterloo", "country": "CA", "linkedin_url": "https://www.linkedin.com/company/simantic", "x_url": "", "fb_url": null, "cb_url": null, "github_url": null, "logo_url": "https://bookface-images.s3.amazonaws.com/small_logos/12eef74104b6e57636a6f0d2305e3a2d18d5c2e5.png", "app_video_url": null, "dday_video_url": null, "company_photos": [], "primary_partner": { "name": "Aaron Epstein", "url": "https://www.ycombinator.com/people/aaron-epstein" }, "founders": [ { "user_id": 3082935, "full_name": "Seungmin Hong", "title": "Founder/CEO", "founder_bio": "Founder at Simantic (YC F26). Previously firmware engineer at Tesla, Simbe Robotics, and Rapyuta Robotics. ML at Ericsson. BASc Computer Engineering from University of Waterloo.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/shong0504", "x_url": "https://x.com/shong0504", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/dc234bdf0e7d060cf24bf13d252ce7311c2e3ce0.jpg" }, { "user_id": 3729139, "full_name": "Ahnaf Shahriar", "title": "Founder/CTO", "founder_bio": "Founder at Simantic (YC F26). Previously Embedded Software Engineer at Neuralink (Implant/Charger) and AI Hardware Engineer at Tesla (Dojo/Autopilot). Computer Engineer from the University of Waterloo.", "is_active": true, "linkedin_url": "https://www.linkedin.com/in/ahnaf-s", "x_url": "https://x.com/enough_ahnaf", "avatar_thumb_url": "https://bookface-images.s3.us-west-2.amazonaws.com/avatars/7d91d8988fc211a1d486d15228c422801d7cf268.jpg" } ], "jobs": [ { "id": 98191, "title": "Lead Simulation Researcher (Electronics / Firmware)", "url": "https://www.ycombinator.com/companies/simantic/jobs/UKriFvb-lead-simulation-researcher-electronics-firmware", "location": "Waterloo, Ontario, CA / San Francisco, CA, US", "type": "Full-time", "role": "Engineering", "role_type": "Electrical", "salary_range": "$200K - $300K", "equity_range": "2.00% - 5.00%", "experience": "6+ years", "visa": "Will sponsor", "skills": [ "Assembly", "C", "C#", "C++", "Verilog", "GPU Programming", "Firmware", "FPGAs" ] } ], "news": [ { "title": "Simantic scales from Waterloo startup to global AI hardware innovator | Waterloo News | University of Waterloo", "url": "https://uwaterloo.ca/news/simantic-scales-waterloo-startup-global-ai-hardware", "date": "Jul 31, 2026" } ], "launches": [] } ]